58 lines
2.2 KiB
Diff
58 lines
2.2 KiB
Diff
From df749cdb015011e9ed8b60ebb84b4e76a9f35735 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Thu, 30 Apr 2020 10:06:24 +0200
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Subject: [PATCH] arm64: dts: marvell: armada-37xx: Move PCIe comphy handle
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property
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Move the comphy handle property of the PCIe node from board specific
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device tree files (EspressoBin and Turris Mox) to the generic
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armada-37xx.dtsi.
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This is correct since this is the only possible PCIe PHY configuration
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on Armada 37xx, so when PCIe is enabled on any board, this handle is
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correct.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 -
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arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 -
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arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
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3 files changed, 1 insertion(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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@@ -56,7 +56,6 @@
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/* J9 */
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&pcie0 {
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status = "okay";
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- phys = <&comphy1 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
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@@ -133,7 +133,6 @@
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status = "okay";
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max-link-speed = <2>;
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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- phys = <&comphy1 0>;
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/*
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* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
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* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@@ -501,6 +501,7 @@
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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+ phys = <&comphy1 0>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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