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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
58 lines
1.5 KiB
Diff
58 lines
1.5 KiB
Diff
From c1619d9de2da093a585426e9cef353ca1789236d Mon Sep 17 00:00:00 2001
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From: Florinel Iordache <florinel.iordache@nxp.com>
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Date: Mon, 5 Nov 2018 17:02:19 +0200
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Subject: [PATCH] arm64: dts: lx2160: PCS PHY definitions for 10GBase-KR and
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40GBase-KR backplane modes
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Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 40 +++++++++++++++++++++++
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1 file changed, 40 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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@@ -162,3 +162,43 @@
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&usb1 {
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status = "okay";
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};
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+
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+&pcs_mdio1 {
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+ pcs_phy1: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ backplane-mode = "40gbase-kr";
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+ reg = <0x0>;
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+ fsl,lane-handle = <&serdes1>;
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+ fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
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+ };
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+};
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+
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+&pcs_mdio2 {
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+ pcs_phy2: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ backplane-mode = "40gbase-kr";
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+ reg = <0x0>;
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+ fsl,lane-handle = <&serdes1>;
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+ fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
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+ };
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+};
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+
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+&pcs_mdio3 {
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+ pcs_phy3: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ backplane-mode = "10gbase-kr";
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+ reg = <0x0>;
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+ fsl,lane-handle = <&serdes1>;
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+ fsl,lane-reg = <0xF00 0x100>; /* lane H */
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+ };
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+};
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+
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+&pcs_mdio4 {
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+ pcs_phy4: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ backplane-mode = "10gbase-kr";
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+ reg = <0x0>;
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+ fsl,lane-handle = <&serdes1>;
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+ fsl,lane-reg = <0xE00 0x100>; /* lane G */
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+ };
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+};
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