108 lines
3.0 KiB
Diff
108 lines
3.0 KiB
Diff
From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Sat, 14 Jan 2023 18:01:29 +0100
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Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce mtk_hw_warm_reset
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support
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Introduce mtk_hw_warm_reset utility routine. This is a preliminary patch
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to align reset procedure to vendor sdk and avoid to power down the chip
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during hw reset.
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Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -3277,7 +3277,54 @@ static void mtk_hw_reset(struct mtk_eth
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0x3ffffff);
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}
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-static int mtk_hw_init(struct mtk_eth *eth)
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+static u32 mtk_hw_reset_read(struct mtk_eth *eth)
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+{
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+ u32 val;
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+
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+ regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
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+ return val;
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+}
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+
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+static void mtk_hw_warm_reset(struct mtk_eth *eth)
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+{
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+ u32 rst_mask, val;
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+
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+ regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
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+ RSTCTRL_FE);
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+ if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
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+ val & RSTCTRL_FE, 1, 1000)) {
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+ dev_err(eth->dev, "warm reset failed\n");
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+ mtk_hw_reset(eth);
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+ return;
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+ }
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+
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
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+ else
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+ rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
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+
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
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+ rst_mask |= RSTCTRL_PPE1;
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+
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+ regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
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+
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+ udelay(1);
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+ val = mtk_hw_reset_read(eth);
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+ if (!(val & rst_mask))
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+ dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
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+ val, rst_mask);
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+
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+ rst_mask |= RSTCTRL_FE;
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+ regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
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+
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+ udelay(1);
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+ val = mtk_hw_reset_read(eth);
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+ if (val & rst_mask)
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+ dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
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+ val, rst_mask);
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+}
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+
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+static int mtk_hw_init(struct mtk_eth *eth, bool reset)
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{
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u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
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ETHSYS_DMA_AG_MAP_PPE;
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@@ -3316,7 +3363,12 @@ static int mtk_hw_init(struct mtk_eth *e
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return 0;
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}
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- mtk_hw_reset(eth);
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+ msleep(100);
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+
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+ if (reset)
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+ mtk_hw_warm_reset(eth);
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+ else
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+ mtk_hw_reset(eth);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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/* Set FE to PDMAv2 if necessary */
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@@ -3507,7 +3559,7 @@ static void mtk_pending_work(struct work
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if (eth->dev->pins)
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pinctrl_select_state(eth->dev->pins->p,
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eth->dev->pins->default_state);
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- mtk_hw_init(eth);
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+ mtk_hw_init(eth, true);
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/* restart DMA and enable IRQs */
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for (i = 0; i < MTK_MAC_COUNT; i++) {
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@@ -4109,7 +4161,7 @@ static int mtk_probe(struct platform_dev
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eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
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INIT_WORK(ð->pending_work, mtk_pending_work);
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- err = mtk_hw_init(eth);
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+ err = mtk_hw_init(eth, false);
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if (err)
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goto err_wed_exit;
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