44 lines
1.5 KiB
Diff
44 lines
1.5 KiB
Diff
From 3f02735e5da5367e4cd563ce6e5c21ce27922248 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Mon, 24 Feb 2020 15:44:26 -0800
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Subject: [PATCH] Revert "net: dsa: bcm_sf2: Also configure Port 5 for 2Gb/sec
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on 7278"
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This reverts commit 7458bd540fa0a90220b9e8c349d910d9dde9caf8 ("net: dsa:
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bcm_sf2: Also configure Port 5 for 2Gb/sec on 7278") as it causes
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advanced congestion buffering issues with 7278 switch devices when using
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their internal Giabit PHY. While this is being debugged, continue with
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conservative defaults that work and do not cause packet loss.
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Fixes: 7458bd540fa0 ("net: dsa: bcm_sf2: Also configure Port 5 for 2Gb/sec on 7278")
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Reviewed-by: Vivien Didelot <vivien.didelot@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/bcm_sf2.c | 3 ---
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drivers/net/dsa/bcm_sf2_regs.h | 1 -
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2 files changed, 4 deletions(-)
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--- a/drivers/net/dsa/bcm_sf2.c
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+++ b/drivers/net/dsa/bcm_sf2.c
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@@ -620,9 +620,6 @@ force_link:
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reg |= RXFLOW_CNTL;
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}
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- if (priv->type == BCM7278_DEVICE_ID && dsa_is_cpu_port(ds, port))
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- reg |= GMIIP_SPEED_UP_2G;
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-
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core_writel(priv, reg, offset);
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}
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--- a/drivers/net/dsa/bcm_sf2_regs.h
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+++ b/drivers/net/dsa/bcm_sf2_regs.h
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@@ -178,7 +178,6 @@ enum bcm_sf2_reg_offs {
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#define RXFLOW_CNTL (1 << 4)
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#define TXFLOW_CNTL (1 << 5)
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#define SW_OVERRIDE (1 << 6)
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-#define GMIIP_SPEED_UP_2G (1 << 7)
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#define CORE_WATCHDOG_CTRL 0x001e4
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#define SOFTWARE_RESET (1 << 7)
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