170 lines
6.9 KiB
Diff
170 lines
6.9 KiB
Diff
From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Mon, 22 Apr 2024 10:15:11 +0300
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Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
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mt753x_to_cpu_fw
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The mt753x_bpdu_port_fw enum is globally used for manipulating the process
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of deciding the forwardable ports, specifically concerning the CPU port(s).
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Therefore, rename it and the values in it to mt753x_to_cpu_fw.
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Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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---
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drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
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drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
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2 files changed, 56 insertions(+), 64 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p
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* VLAN-untagged.
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*/
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mt7530_rmw(priv, MT753X_BPC,
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- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
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- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
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- MT753X_BPDU_PORT_FW_MASK,
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- MT753X_PAE_BPDU_FR |
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- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
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- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_BPDU_CPU_ONLY);
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+ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
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+ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
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+ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
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+ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ TO_CPU_FW_CPU_ONLY);
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/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
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* them VLAN-untagged.
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*/
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mt7530_rmw(priv, MT753X_RGAC1,
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- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
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- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
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- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
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- MT753X_R02_BPDU_FR |
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- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
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- MT753X_R01_BPDU_FR |
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- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_BPDU_CPU_ONLY);
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+ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
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+ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
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+ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
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+ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ TO_CPU_FW_CPU_ONLY);
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/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
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* them VLAN-untagged.
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*/
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mt7530_rmw(priv, MT753X_RGAC2,
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- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
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- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
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- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
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- MT753X_R0E_BPDU_FR |
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- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
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- MT753X_R03_BPDU_FR |
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- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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- MT753X_BPDU_CPU_ONLY);
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+ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
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+ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
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+ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
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+ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
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+ TO_CPU_FW_CPU_ONLY);
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}
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static void
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -67,47 +67,47 @@ enum mt753x_id {
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#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
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MT7531_MIRROR_MASK : MIRROR_MASK)
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-/* Registers for BPDU and PAE frame control*/
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+/* Register for BPDU and PAE frame control */
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#define MT753X_BPC 0x24
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-#define MT753X_PAE_BPDU_FR BIT(25)
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-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
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-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
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-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
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-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
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-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
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-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
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-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
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+#define PAE_BPDU_FR BIT(25)
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+#define PAE_EG_TAG_MASK GENMASK(24, 22)
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+#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
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+#define PAE_PORT_FW_MASK GENMASK(18, 16)
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+#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
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+#define BPDU_EG_TAG_MASK GENMASK(8, 6)
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+#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
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+#define BPDU_PORT_FW_MASK GENMASK(2, 0)
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-/* Register for :01 and :02 MAC DA frame control */
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+/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
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#define MT753X_RGAC1 0x28
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-#define MT753X_R02_BPDU_FR BIT(25)
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-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
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-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
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-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
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-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
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-#define MT753X_R01_BPDU_FR BIT(9)
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-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
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-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
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-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
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+#define R02_BPDU_FR BIT(25)
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+#define R02_EG_TAG_MASK GENMASK(24, 22)
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+#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
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+#define R02_PORT_FW_MASK GENMASK(18, 16)
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+#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
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+#define R01_BPDU_FR BIT(9)
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+#define R01_EG_TAG_MASK GENMASK(8, 6)
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+#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
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+#define R01_PORT_FW_MASK GENMASK(2, 0)
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-/* Register for :03 and :0E MAC DA frame control */
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+/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
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#define MT753X_RGAC2 0x2c
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-#define MT753X_R0E_BPDU_FR BIT(25)
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-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
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-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
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-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
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-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
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-#define MT753X_R03_BPDU_FR BIT(9)
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-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
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-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
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-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
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+#define R0E_BPDU_FR BIT(25)
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+#define R0E_EG_TAG_MASK GENMASK(24, 22)
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+#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
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+#define R0E_PORT_FW_MASK GENMASK(18, 16)
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+#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
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+#define R03_BPDU_FR BIT(9)
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+#define R03_EG_TAG_MASK GENMASK(8, 6)
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+#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
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+#define R03_PORT_FW_MASK GENMASK(2, 0)
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-enum mt753x_bpdu_port_fw {
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- MT753X_BPDU_FOLLOW_MFC,
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- MT753X_BPDU_CPU_EXCLUDE = 4,
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- MT753X_BPDU_CPU_INCLUDE = 5,
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- MT753X_BPDU_CPU_ONLY = 6,
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- MT753X_BPDU_DROP = 7,
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+enum mt753x_to_cpu_fw {
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+ TO_CPU_FW_SYSTEM_DEFAULT,
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+ TO_CPU_FW_CPU_EXCLUDE = 4,
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+ TO_CPU_FW_CPU_INCLUDE = 5,
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+ TO_CPU_FW_CPU_ONLY = 6,
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+ TO_CPU_FW_DROP = 7,
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};
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/* Registers for address table access */
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