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openwrt/target/linux/layerscape/patches-5.4/701-net-0318-staging-fsl_ppfe-eth-adapt-to-link-mode-based-phydev.patch
Yangbo Lu cddd459140 layerscape: add patches-5.4
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-05-07 12:53:06 +02:00

57 lines
2.1 KiB
Diff

From 002297dd2634e993257a00fe4458b0288ec7baea Mon Sep 17 00:00:00 2001
From: Calvin Johnson <calvin.johnson@nxp.com>
Date: Wed, 27 Mar 2019 13:25:57 +0530
Subject: [PATCH] staging: fsl_ppfe/eth: adapt to link mode based phydev
changes
Setting link mode bits have changed with the integration of
commit (3c1bcc8 net: ethernet: Convert phydev advertize and
supported from u32 to link mode). Adapt to the new method of
setting and clearing the link mode bits.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
drivers/staging/fsl_ppfe/pfe_eth.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
--- a/drivers/staging/fsl_ppfe/pfe_eth.c
+++ b/drivers/staging/fsl_ppfe/pfe_eth.c
@@ -701,10 +701,14 @@ static int pfe_eth_set_pauseparam(struct
EGPI_PAUSE_ENABLE),
priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
if (priv->phydev) {
- priv->phydev->supported |= ADVERTISED_Pause |
- ADVERTISED_Asym_Pause;
- priv->phydev->advertising |= ADVERTISED_Pause |
- ADVERTISED_Asym_Pause;
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ priv->phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ priv->phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ priv->phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ priv->phydev->advertising);
}
} else {
gemac_disable_pause_rx(priv->EMAC_baseaddr);
@@ -712,10 +716,14 @@ static int pfe_eth_set_pauseparam(struct
~EGPI_PAUSE_ENABLE),
priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
if (priv->phydev) {
- priv->phydev->supported &= ~(ADVERTISED_Pause |
- ADVERTISED_Asym_Pause);
- priv->phydev->advertising &= ~(ADVERTISED_Pause |
- ADVERTISED_Asym_Pause);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ priv->phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ priv->phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ priv->phydev->advertising);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ priv->phydev->advertising);
}
}