mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-06-14 19:23:53 +02:00
9501ce909f
This fixes a kernel build problem.
The removed parts of the patch are already applied upstream.
Fixes: 9ad3ef27b9 ("kernel: bump 5.4 to 5.4.153")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From 7e64c4e922cddea72dacd3f0d8f395d9182ea5bc Mon Sep 17 00:00:00 2001
|
|
From: Wen He <wen.he_1@nxp.com>
|
|
Date: Mon, 14 Oct 2019 15:13:27 +0800
|
|
Subject: [PATCH] arm64: dts: ls1028a: Update #clock-cells of dpclk node
|
|
|
|
Update the property #clock-cells = <1> to #clock-cells = <0> of the
|
|
dpclk, since the Display output pixel clock driver provides single
|
|
clock output.
|
|
|
|
Signed-off-by: Wen He <wen.he_1@nxp.com>
|
|
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
---
|
|
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++--
|
|
1 file changed, 2 insertions(+), 2 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
|
@@ -86,7 +86,7 @@
|
|
dpclk: clock-controller@f1f0000 {
|
|
compatible = "fsl,ls1028a-plldig";
|
|
reg = <0x0 0xf1f0000 0x0 0xffff>;
|
|
- #clock-cells = <1>;
|
|
+ #clock-cells = <0>;
|
|
clocks = <&osc_27m>;
|
|
};
|
|
|
|
@@ -846,7 +846,7 @@
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "DE", "SE";
|
|
- clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
|
|
+ clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
|
|
<&clockgen 2 2>;
|
|
clock-names = "pxlclk", "mclk", "aclk", "pclk";
|
|
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
|