189 lines
5.7 KiB
Diff
189 lines
5.7 KiB
Diff
From db6d450ea27bd6e355561539c0eedaa54c923471 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 14:20:15 +0000
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Subject: [PATCH] clk: bcm2835: expose raw clock-registers via debugfs
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For debugging purposes under some circumstance
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it helps to be able to see the actual clock registers.
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E.g: when looking at the clock divider it is helpful to
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see what the actual clock divider is.
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This patch exposes all the clock registers specific to each
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clock/pll/pll-divider via debugfs.
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Acked-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 96bf9c69d5729781018a00f08e2ae395ec3346b4)
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---
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drivers/clk/bcm/clk-bcm2835.c | 101 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 101 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -37,6 +37,7 @@
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/bcm2835.h>
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+#include <linux/debugfs.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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@@ -313,6 +314,27 @@ static inline u32 cprman_read(struct bcm
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return readl(cprman->regs + reg);
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}
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+static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
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+ struct debugfs_reg32 *regs, size_t nregs,
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+ struct dentry *dentry)
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+{
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+ struct dentry *regdump;
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+ struct debugfs_regset32 *regset;
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+
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+ regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
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+ if (!regset)
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+ return -ENOMEM;
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+
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+ regset->regs = regs;
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+ regset->nregs = nregs;
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+ regset->base = cprman->regs + base;
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+
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+ regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
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+ regset);
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+
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+ return regdump ? 0 : -ENOMEM;
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+}
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+
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/*
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* These are fixed clocks. They're probably not all root clocks and it may
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* be possible to turn them on and off but until this is mapped out better
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@@ -1050,6 +1072,36 @@ static int bcm2835_pll_set_rate(struct c
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return 0;
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}
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+static int bcm2835_pll_debug_init(struct clk_hw *hw,
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+ struct dentry *dentry)
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+{
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+ struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
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+ struct bcm2835_cprman *cprman = pll->cprman;
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+ const struct bcm2835_pll_data *data = pll->data;
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+ struct debugfs_reg32 *regs;
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+
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+ regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
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+ if (!regs)
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+ return -ENOMEM;
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+
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+ regs[0].name = "cm_ctrl";
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+ regs[0].offset = data->cm_ctrl_reg;
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+ regs[1].name = "a2w_ctrl";
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+ regs[1].offset = data->a2w_ctrl_reg;
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+ regs[2].name = "frac";
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+ regs[2].offset = data->frac_reg;
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+ regs[3].name = "ana0";
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+ regs[3].offset = data->ana_reg_base + 0 * 4;
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+ regs[4].name = "ana1";
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+ regs[4].offset = data->ana_reg_base + 1 * 4;
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+ regs[5].name = "ana2";
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+ regs[5].offset = data->ana_reg_base + 2 * 4;
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+ regs[6].name = "ana3";
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+ regs[6].offset = data->ana_reg_base + 3 * 4;
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+
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+ return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
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+}
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+
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static const struct clk_ops bcm2835_pll_clk_ops = {
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.is_prepared = bcm2835_pll_is_on,
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.prepare = bcm2835_pll_on,
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@@ -1057,6 +1109,7 @@ static const struct clk_ops bcm2835_pll_
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.recalc_rate = bcm2835_pll_get_rate,
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.set_rate = bcm2835_pll_set_rate,
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.round_rate = bcm2835_pll_round_rate,
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+ .debug_init = bcm2835_pll_debug_init,
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};
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struct bcm2835_pll_divider {
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@@ -1159,6 +1212,26 @@ static int bcm2835_pll_divider_set_rate(
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return 0;
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}
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+static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
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+ struct dentry *dentry)
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+{
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+ struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
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+ struct bcm2835_cprman *cprman = divider->cprman;
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+ const struct bcm2835_pll_divider_data *data = divider->data;
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+ struct debugfs_reg32 *regs;
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+
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+ regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
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+ if (!regs)
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+ return -ENOMEM;
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+
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+ regs[0].name = "cm";
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+ regs[0].offset = data->cm_reg;
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+ regs[1].name = "a2w";
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+ regs[1].offset = data->a2w_reg;
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+
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+ return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
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+}
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+
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static const struct clk_ops bcm2835_pll_divider_clk_ops = {
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.is_prepared = bcm2835_pll_divider_is_on,
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.prepare = bcm2835_pll_divider_on,
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@@ -1166,6 +1239,7 @@ static const struct clk_ops bcm2835_pll_
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.recalc_rate = bcm2835_pll_divider_get_rate,
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.set_rate = bcm2835_pll_divider_set_rate,
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.round_rate = bcm2835_pll_divider_round_rate,
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+ .debug_init = bcm2835_pll_divider_debug_init,
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};
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/*
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@@ -1407,6 +1481,31 @@ static u8 bcm2835_clock_get_parent(struc
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return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
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}
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+static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
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+ {
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+ .name = "ctl",
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+ .offset = 0,
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+ },
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+ {
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+ .name = "div",
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+ .offset = 4,
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+ },
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+};
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+
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+static int bcm2835_clock_debug_init(struct clk_hw *hw,
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+ struct dentry *dentry)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct bcm2835_cprman *cprman = clock->cprman;
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+ const struct bcm2835_clock_data *data = clock->data;
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+
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+ return bcm2835_debugfs_regset(
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+ cprman, data->ctl_reg,
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+ bcm2835_debugfs_clock_reg32,
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+ ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
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+ dentry);
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+}
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+
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static const struct clk_ops bcm2835_clock_clk_ops = {
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.is_prepared = bcm2835_clock_is_on,
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.prepare = bcm2835_clock_on,
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@@ -1416,6 +1515,7 @@ static const struct clk_ops bcm2835_cloc
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.determine_rate = bcm2835_clock_determine_rate,
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.set_parent = bcm2835_clock_set_parent,
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.get_parent = bcm2835_clock_get_parent,
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+ .debug_init = bcm2835_clock_debug_init,
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};
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static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
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@@ -1434,6 +1534,7 @@ static const struct clk_ops bcm2835_vpu_
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.determine_rate = bcm2835_clock_determine_rate,
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.set_parent = bcm2835_clock_set_parent,
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.get_parent = bcm2835_clock_get_parent,
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+ .debug_init = bcm2835_clock_debug_init,
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};
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static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
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