36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From 7e64c4e922cddea72dacd3f0d8f395d9182ea5bc Mon Sep 17 00:00:00 2001
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From: Wen He <wen.he_1@nxp.com>
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Date: Mon, 14 Oct 2019 15:13:27 +0800
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Subject: [PATCH] arm64: dts: ls1028a: Update #clock-cells of dpclk node
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Update the property #clock-cells = <1> to #clock-cells = <0> of the
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dpclk, since the Display output pixel clock driver provides single
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clock output.
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Signed-off-by: Wen He <wen.he_1@nxp.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -86,7 +86,7 @@
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dpclk: clock-controller@f1f0000 {
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compatible = "fsl,ls1028a-plldig";
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reg = <0x0 0xf1f0000 0x0 0xffff>;
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- #clock-cells = <1>;
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+ #clock-cells = <0>;
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clocks = <&osc_27m>;
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};
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@@ -846,7 +846,7 @@
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interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
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<0 223 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "DE", "SE";
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- clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
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+ clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
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<&clockgen 2 2>;
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clock-names = "pxlclk", "mclk", "aclk", "pclk";
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arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
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