122 lines
4.1 KiB
Diff
122 lines
4.1 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Tue, 31 Jan 2017 22:54:54 +0100
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Subject: [PATCH] net: phy: broadcom: rehook BCM54612E specific init
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This extra BCM54612E code in PHY driver isn't really aneg specific. Even
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without it aneg works OK but the problem is no packets pass through PHY.
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Moreover putting this code inside config_aneg callback didn't allow
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resuming PHY correctly. When driver called phy_stop and phy_start it was
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putting PHY machine into RESUMING state. After that machine was
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switching into AN and NOLINK without ever calling phy_start_aneg. This
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prevented this extra setup from being called and PHY didn't work.
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This change has been verified to fix network on BCM47186B0 SoC device
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with BCM54612E.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/phy/broadcom.c
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+++ b/drivers/net/phy/broadcom.c
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@@ -46,6 +46,34 @@ static int bcm54210e_config_init(struct
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return 0;
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}
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+static int bcm54612e_config_init(struct phy_device *phydev)
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+{
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+ /* Clear TX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
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+ /* Disable TXD to GTXCLK clock delay (default set) */
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+ /* Bit 9 is the only field in shadow register 00011 */
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+ bcm_phy_write_shadow(phydev, 0x03, 0);
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+ }
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+
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+ /* Clear RX internal delay unless requested. */
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+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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+ u16 reg;
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+
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+ reg = bcm54xx_auxctl_read(phydev,
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+ MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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+ /* Disable RXD to RXC delay (default set) */
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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+ /* Clear shadow selector field */
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+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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+ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
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+ }
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+
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+ return 0;
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+}
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+
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static int bcm54810_config(struct phy_device *phydev)
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{
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int rc, val;
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@@ -250,6 +278,10 @@ static int bcm54xx_config_init(struct ph
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err = bcm54210e_config_init(phydev);
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if (err)
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return err;
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+ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
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+ err = bcm54612e_config_init(phydev);
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+ if (err)
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+ return err;
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} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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err = bcm54810_config(phydev);
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if (err)
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@@ -395,39 +427,6 @@ static int bcm5481_config_aneg(struct ph
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return ret;
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}
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-static int bcm54612e_config_aneg(struct phy_device *phydev)
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-{
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- int ret;
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-
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- /* First, auto-negotiate. */
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- ret = genphy_config_aneg(phydev);
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-
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- /* Clear TX internal delay unless requested. */
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- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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- (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
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- /* Disable TXD to GTXCLK clock delay (default set) */
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- /* Bit 9 is the only field in shadow register 00011 */
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- bcm_phy_write_shadow(phydev, 0x03, 0);
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- }
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-
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- /* Clear RX internal delay unless requested. */
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- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
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- (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
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- u16 reg;
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-
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- reg = bcm54xx_auxctl_read(phydev,
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- MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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- /* Disable RXD to RXC delay (default set) */
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- reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
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- /* Clear shadow selector field */
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- reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
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- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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- MII_BCM54XX_AUXCTL_MISC_WREN | reg);
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- }
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-
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- return ret;
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-}
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-
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static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
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{
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int val;
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@@ -594,7 +593,7 @@ static struct phy_driver broadcom_driver
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = bcm54xx_config_init,
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- .config_aneg = bcm54612e_config_aneg,
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+ .config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = bcm_phy_ack_intr,
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.config_intr = bcm_phy_config_intr,
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