28 lines
1.1 KiB
Diff
28 lines
1.1 KiB
Diff
From 59938610a705283fef63447c7e777781358610e2 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 11 Feb 2021 18:37:04 +0000
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Subject: [PATCH] drm/vc4: Correct pixel order for DSI0
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For slightly unknown reasons, dsi0 takes a different pixel format
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to dsi1, and that has to be set in the pixel valve.
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Amend the setup accordingly.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -319,7 +319,8 @@ static void vc4_crtc_config_pv(struct dr
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u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
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bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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- u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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+ bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
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+ u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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u8 ppc = pv_data->pixels_per_clock;
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bool debug_dump_regs = false;
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