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8299d1f057
Rebased RPi foundation patches on linux 5.10.59, removed applied and reverted patches, wireless patches and defconfig patches. bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 4B v1.1 4G bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 264515dcb2a318072530a2171c084dc207006399 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 30 Nov 2020 16:16:03 +0000
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Subject: [PATCH] drm/vc4: Correct DSI register definition
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The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
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definitions were swapped, so trying to use more than a single data
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lane failed as lane 1 would get powered down.
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(In theory a 4 lane device would work as all lanes would remain
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powered).
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Correct the definitions.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -306,11 +306,11 @@
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# define DSI0_PHY_AFEC0_RESET BIT(11)
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# define DSI1_PHY_AFEC0_PD_BG BIT(11)
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# define DSI0_PHY_AFEC0_PD BIT(10)
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-# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
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+# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
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# define DSI0_PHY_AFEC0_PD_BG BIT(9)
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# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
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# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
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-# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
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+# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
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# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
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# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
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# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
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