82 lines
2.5 KiB
Diff
82 lines
2.5 KiB
Diff
From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 19 Jun 2023 06:09:35 +0200
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Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
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A properly clock driver for ralink SoCs has been added. Hence there is no
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need to have clock related code in 'arch/mips/ralink' folder anymore.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
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arch/mips/ralink/rt288x.c | 31 ------------------------------
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2 files changed, 41 deletions(-)
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--- a/arch/mips/include/asm/mach-ralink/rt288x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
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@@ -17,7 +17,6 @@
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_CHIP_ID 0x0c
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#define SYSC_REG_SYSTEM_CONFIG 0x10
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-#define SYSC_REG_CLKCFG 0x30
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#define RT2880_CHIP_NAME0 0x38325452
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#define RT2880_CHIP_NAME1 0x20203038
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@@ -26,15 +25,6 @@
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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-#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
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-#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
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-#define SYSTEM_CONFIG_CPUCLK_250 0x0
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-#define SYSTEM_CONFIG_CPUCLK_266 0x1
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-#define SYSTEM_CONFIG_CPUCLK_280 0x2
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-#define SYSTEM_CONFIG_CPUCLK_300 0x3
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-
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-#define CLKCFG_SRAM_CS_N_WDT BIT(9)
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-
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#define RT2880_SDRAM_BASE 0x08000000
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#define RT2880_MEM_SIZE_MIN 2
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#define RT2880_MEM_SIZE_MAX 128
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--- a/arch/mips/ralink/rt288x.c
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+++ b/arch/mips/ralink/rt288x.c
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@@ -17,37 +17,6 @@
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#include "common.h"
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-void __init ralink_clk_init(void)
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-{
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- unsigned long cpu_rate, wmac_rate = 40000000;
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- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
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-
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- switch (t) {
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- case SYSTEM_CONFIG_CPUCLK_250:
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- cpu_rate = 250000000;
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- break;
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- case SYSTEM_CONFIG_CPUCLK_266:
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- cpu_rate = 266666667;
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- break;
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- case SYSTEM_CONFIG_CPUCLK_280:
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- cpu_rate = 280000000;
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- break;
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- case SYSTEM_CONFIG_CPUCLK_300:
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- cpu_rate = 300000000;
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- break;
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- }
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-
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- ralink_clk_add("cpu", cpu_rate);
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- ralink_clk_add("300100.timer", cpu_rate / 2);
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- ralink_clk_add("300120.watchdog", cpu_rate / 2);
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- ralink_clk_add("300500.uart", cpu_rate / 2);
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- ralink_clk_add("300900.i2c", cpu_rate / 2);
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- ralink_clk_add("300c00.uartlite", cpu_rate / 2);
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- ralink_clk_add("400000.ethernet", cpu_rate / 2);
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- ralink_clk_add("480000.wmac", wmac_rate);
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-}
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-
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
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