101 lines
3.9 KiB
Diff
101 lines
3.9 KiB
Diff
From 7f3e55a3890fa26d15e2e4e90213962d1a7f6df9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 12 Feb 2021 20:32:55 +0100
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Subject: [PATCH] PCI: aardvark: Add support for ERR interrupt on emulated
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bridge
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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ERR interrupt is triggered when corresponding bit is unmasked in both ISR0
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and PCI_EXP_DEVCTL registers. Unmasking ERR bits in PCI_EXP_DEVCTL register
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is not enough. This means that currently the ERR interrupt is never
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triggered.
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Unmask ERR bits in ISR0 register at driver probe time. ERR interrupt is not
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triggered until ERR bits are unmasked also in PCI_EXP_DEVCTL register,
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which is done by AER driver. So it is safe to unconditionally unmask all
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ERR bits in aardvark probe.
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Aardvark HW sets PCI_ERR_ROOT_AER_IRQ to zero and when corresponding bits
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in ISR0 and PCI_EXP_DEVCTL are enabled, the HW triggers a generic interrupt
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on GIC. Chain this interrupt to PCIe interrupt 0 with
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generic_handle_domain_irq() to allow processing of ERR interrupts.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 36 ++++++++++++++++++++++++++-
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1 file changed, 35 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -97,6 +97,10 @@
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#define PCIE_MSG_PM_PME_MASK BIT(7)
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#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
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#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
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+#define PCIE_ISR0_CORR_ERR BIT(11)
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+#define PCIE_ISR0_NFAT_ERR BIT(12)
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+#define PCIE_ISR0_FAT_ERR BIT(13)
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+#define PCIE_ISR0_ERR_MASK GENMASK(13, 11)
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#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
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#define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
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#define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
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@@ -785,11 +789,15 @@ advk_pci_bridge_emul_base_conf_read(stru
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case PCI_INTERRUPT_LINE: {
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/*
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* From the whole 32bit register we support reading from HW only
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- * one bit: PCI_BRIDGE_CTL_BUS_RESET.
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+ * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR.
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* Other bits are retrieved only from emulated config buffer.
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*/
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__le32 *cfgspace = (__le32 *)&bridge->conf;
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u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
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+ if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)
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+ val &= ~(PCI_BRIDGE_CTL_SERR << 16);
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+ else
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+ val |= PCI_BRIDGE_CTL_SERR << 16;
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if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
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val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
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else
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@@ -815,6 +823,19 @@ advk_pci_bridge_emul_base_conf_write(str
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break;
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case PCI_INTERRUPT_LINE:
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+ /*
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+ * According to Figure 6-3: Pseudo Logic Diagram for Error
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+ * Message Controls in PCIe base specification, SERR# Enable bit
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+ * in Bridge Control register enable receiving of ERR_* messages
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+ */
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+ if (mask & (PCI_BRIDGE_CTL_SERR << 16)) {
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+ u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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+ if (new & (PCI_BRIDGE_CTL_SERR << 16))
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+ val &= ~PCIE_ISR0_ERR_MASK;
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+ else
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+ val |= PCIE_ISR0_ERR_MASK;
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+ advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
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+ }
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if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
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u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
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if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
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@@ -1464,6 +1485,19 @@ static void advk_pcie_handle_int(struct
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isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
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+ /* Process ERR interrupt */
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+ if (isr0_status & PCIE_ISR0_ERR_MASK) {
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+ advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
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+
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+ /*
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+ * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use
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+ * PCIe interrupt 0
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+ */
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+ virq = irq_find_mapping(pcie->irq_domain, 0);
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+ if (generic_handle_irq(virq) == -EINVAL)
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+ dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n");
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+ }
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+
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/* Process MSI interrupts */
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if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
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advk_pcie_handle_msi(pcie);
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