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5e91b4507c
The default location of tfa-layerscape has been changed from codeuaurora to github. Also use the latest tag for Layerscape Linux Development POC from NXP. v2: * restored ls1021a-afrdm board * added platform defines to fiptool so ls-ddr-phy can be built Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch> (reset PKG_RELEASE) Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
233 lines
5.9 KiB
Diff
233 lines
5.9 KiB
Diff
From 8c6a66feb721f18c930c7df03d1fbb7304107af6 Mon Sep 17 00:00:00 2001
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From: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch>
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Date: Thu, 20 Apr 2023 16:21:25 +0200
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Subject: [PATCH] tfa-layerscape: Restore ls1012afrdm support
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Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch>
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---
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plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c | 34 +++++++
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plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 92 +++++++++++++++++++
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plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk | 25 +++++
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.../soc-ls1012a/ls1012afrdm/platform_def.h | 13 +++
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plat/nxp/soc-ls1012a/ls1012afrdm/policy.h | 16 ++++
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5 files changed, 180 insertions(+)
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create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
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create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
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create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
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create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
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create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
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diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
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new file mode 100644
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index 000000000..8cb518540
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--- /dev/null
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+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
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@@ -0,0 +1,34 @@
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+/*
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+ * Copyright 2018-2022 NXP
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+
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+#include <common/debug.h>
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+#include <fsl_mmdc.h>
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+
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+#include <platform_def.h>
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+
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+long long init_ddr(void)
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+{
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+ static const struct fsl_mmdc_info mparam = {
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+ .mdctl = U(0x04180000),
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+ .mdpdc = U(0x00030035),
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+ .mdotc = U(0x12554000),
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+ .mdcfg0 = U(0xbabf7954),
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+ .mdcfg1 = U(0xdb328f64),
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+ .mdcfg2 = U(0x01ff00db),
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+ .mdmisc = U(0x00001680),
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+ .mdref = U(0x0f3c8000),
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+ .mdrwd = U(0x00002000),
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+ .mdor = U(0x00bf1023),
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+ .mdasp = U(0x0000003f),
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+ .mpodtctrl = U(0x0000022a),
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+ .mpzqhwctrl = U(0xa1390003),
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+ };
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+
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+ mmdc_init(&mparam, NXP_DDR_ADDR);
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+ NOTICE("DDR Init Done\n");
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+
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+ return NXP_DRAM0_SIZE;
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+}
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diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
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new file mode 100644
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index 000000000..eb745a0a3
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--- /dev/null
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+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
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@@ -0,0 +1,92 @@
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+/*
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+ * Copyright 2022 NXP
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+
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+#ifndef PLAT_DEF_H
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+#define PLAT_DEF_H
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+
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+#include <arch.h>
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+/*
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+ * Required without TBBR.
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+ * To include the defines for DDR PHY
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+ * Images.
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+ */
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+#include <tbbr_img_def.h>
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+
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+#include <policy.h>
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+#include <soc.h>
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+
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+/* DDR Related definition */
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+#define PLAT_DEF_DRAM0_SIZE 0x20000000 /* 512 MB */
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+
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+#define NXP_SYSCLK_FREQ 125000000
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+#define NXP_DDRCLK_FREQ 100000000
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+
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+/* UART related definition */
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+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
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+#define NXP_CONSOLE_BAUDRATE 115200
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+
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+#define NXP_SPD_EEPROM0 0x51
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+
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+/* Size of cacheable stacks */
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+#if defined(IMAGE_BL2)
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+#if defined(TRUSTED_BOARD_BOOT)
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+#define PLATFORM_STACK_SIZE 0x2000
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+#else
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+#define PLATFORM_STACK_SIZE 0x1000
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+#endif
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+#elif defined(IMAGE_BL31)
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+#define PLATFORM_STACK_SIZE 0x1000
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+#endif
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+
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+/* SD block buffer */
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+#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
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+#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
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+
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+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
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+
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+/* IO defines as needed by IO driver framework */
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+#define MAX_IO_DEVICES 3
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+#define MAX_IO_BLOCK_DEVICES 1
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+#define MAX_IO_HANDLES 4
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+
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+/*
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+ * FIP image defines - Offset at which FIP Image would be present
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+ * Image would include Bl31 , Bl33 and Bl32 (optional)
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+ */
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+#ifdef POLICY_FUSE_PROVISION
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+#define MAX_FIP_DEVICES 2
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+#endif
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+
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+#ifndef MAX_FIP_DEVICES
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+#define MAX_FIP_DEVICES 1
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+#endif
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+
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+#ifdef PLAT_FIP_OFFSET
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+#undef PLAT_FIP_OFFSET
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+#endif
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+#ifdef PLAT_FIP_MAX_SIZE
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+#undef PLAT_FIP_MAX_SIZE
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+#endif
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+#define PLAT_FIP_OFFSET 0x60000
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+#define PLAT_FIP_MAX_SIZE 0x170000
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+
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+/*
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+ * ID of the secure physical generic timer interrupt used by the BL32.
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+ */
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+#define BL32_IRQ_SEC_PHY_TIMER 29
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+
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+/*
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+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
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+ * as Group 0 interrupts.
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+ */
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+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
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+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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+ GIC_INTR_CFG_LEVEL)
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+
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+#define PLAT_LS_G0_IRQ_PROPS(grp)
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+
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+#endif
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diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
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new file mode 100644
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index 000000000..270e92420
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--- /dev/null
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+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
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@@ -0,0 +1,25 @@
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+#
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+# Copyright 2018-2022 NXP
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+#
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+# SPDX-License-Identifier: BSD-3-Clause
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+#
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+
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+# board-specific build parameters
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+BOOT_MODE := qspi
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+BOARD := ls1012afrdm
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+
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+# DDR Compilation Configs
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+DDRC_NUM_CS := 1
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+
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+# On-Board Flash Details
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+QSPI_FLASH_SZ := 0x4000000
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+
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+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c
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+
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+SUPPORTED_BOOT_MODE := qspi
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+
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+# Adding platform board build info
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+include plat/nxp/common/plat_make_helper/plat_common_def.mk
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+
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+# Adding SoC build info
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+include plat/nxp/soc-ls1012a/soc.mk
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diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
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new file mode 100644
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index 000000000..7daf1c02c
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--- /dev/null
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+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
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@@ -0,0 +1,13 @@
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+/*
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+ * Copyright 2022 NXP
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+
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+#ifndef PLATFORM_DEF_H
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+#define PLATFORM_DEF_H
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+
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+#include <plat_def.h>
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+#include <plat_default_def.h>
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+
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+#endif /* PLATFORM_DEF_H */
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diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
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new file mode 100644
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index 000000000..a782d01c7
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--- /dev/null
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+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
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@@ -0,0 +1,16 @@
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+/*
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+ * Copyright 2018-2022 NXP
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+
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+#ifndef POLICY_H
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+#define POLICY_H
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+
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+/*
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+ * Set this to 0x0 to leave the default SMMU page size in sACR
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+ * Set this to 0x1 to change the SMMU page size to 64K
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+ */
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+#define POLICY_SMMU_PAGESZ_64K 0x0
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+
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+#endif /* POLICY_H */
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--
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2.34.1
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