109 lines
3.5 KiB
Diff
109 lines
3.5 KiB
Diff
From 9d00118e0ac420d3bf6e266a0fbfd28135cbadb8 Mon Sep 17 00:00:00 2001
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From: Shengjiu Wang <shengjiu.wang@nxp.com>
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Date: Thu, 12 Oct 2017 14:01:19 +0800
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Subject: [PATCH] MLK-13946-3: ASoC: fsl_sai: fix the xMR setting
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When there is multi data line enabled, the xMR setting is
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wrong if according to the channel number. which should
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according to the slot number
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Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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---
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sound/soc/fsl/fsl_sai.c | 28 ++++++++++++++++++++++++++--
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sound/soc/fsl/fsl_sai.h | 12 ++++++++++++
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2 files changed, 38 insertions(+), 2 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -80,7 +80,7 @@ static struct fsl_sai_soc_data fsl_sai_i
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static struct fsl_sai_soc_data fsl_sai_imx8qm = {
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.imx = true,
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- .dataline = 0x3,
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+ .dataline = 0xf,
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.fifos = 1,
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.fifo_depth = 64,
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.flags = 0,
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@@ -572,7 +572,7 @@ static int fsl_sai_hw_params(struct snd_
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regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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- regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
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+ regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << slots) - 1));
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return 0;
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}
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@@ -859,11 +859,23 @@ static bool fsl_sai_readable_reg(struct
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switch (reg) {
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case FSL_SAI_TFR0:
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case FSL_SAI_TFR1:
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+ case FSL_SAI_TFR2:
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+ case FSL_SAI_TFR3:
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+ case FSL_SAI_TFR4:
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+ case FSL_SAI_TFR5:
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+ case FSL_SAI_TFR6:
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+ case FSL_SAI_TFR7:
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case FSL_SAI_TMR:
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case FSL_SAI_RDR0:
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case FSL_SAI_RDR1:
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case FSL_SAI_RFR0:
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case FSL_SAI_RFR1:
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+ case FSL_SAI_RFR2:
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+ case FSL_SAI_RFR3:
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+ case FSL_SAI_RFR4:
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+ case FSL_SAI_RFR5:
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+ case FSL_SAI_RFR6:
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+ case FSL_SAI_RFR7:
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case FSL_SAI_RMR:
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return true;
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default:
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@@ -882,8 +894,20 @@ static bool fsl_sai_volatile_reg(struct
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switch (reg) {
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case FSL_SAI_TFR0:
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case FSL_SAI_TFR1:
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+ case FSL_SAI_TFR2:
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+ case FSL_SAI_TFR3:
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+ case FSL_SAI_TFR4:
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+ case FSL_SAI_TFR5:
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+ case FSL_SAI_TFR6:
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+ case FSL_SAI_TFR7:
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case FSL_SAI_RFR0:
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case FSL_SAI_RFR1:
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+ case FSL_SAI_RFR2:
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+ case FSL_SAI_RFR3:
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+ case FSL_SAI_RFR4:
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+ case FSL_SAI_RFR5:
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+ case FSL_SAI_RFR6:
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+ case FSL_SAI_RFR7:
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case FSL_SAI_RDR0:
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case FSL_SAI_RDR1:
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return true;
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--- a/sound/soc/fsl/fsl_sai.h
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+++ b/sound/soc/fsl/fsl_sai.h
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@@ -24,6 +24,12 @@
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#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data */
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#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO */
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#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO */
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+#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO */
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#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
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#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
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#define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
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@@ -36,6 +42,12 @@
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#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data */
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#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO */
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#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO */
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+#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO */
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+#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO */
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+#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO */
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+#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO */
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+#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO */
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+#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO */
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#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
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#define FSL_SAI_xCSR(tx, off) (tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))
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