57 lines
2.1 KiB
Diff
57 lines
2.1 KiB
Diff
From 0b33246dfb59df34b2b834eb00f7aea75cbd4366 Mon Sep 17 00:00:00 2001
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From: Zidan Wang <zidan.wang@freescale.com>
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Date: Mon, 9 Nov 2015 19:03:13 +0800
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Subject: [PATCH] ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode
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For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
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generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
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RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
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error sometimes.
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Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
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Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
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Signed-off-by: Mark Brown <broonie@kernel.org>
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(cherry picked from commit 51659ca069ce5bdf20675a7967a39ef8419e87f2)
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---
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sound/soc/fsl/fsl_sai.c | 29 +++++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -477,6 +477,35 @@ static int fsl_sai_hw_params(struct snd_
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}
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}
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+ /*
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+ * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
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+ * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
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+ * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
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+ * error.
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+ */
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+
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+ if (!sai->is_slave_mode) {
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+ if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
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+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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+ val_cr4);
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
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+ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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+ FSL_SAI_CR5_FBT_MASK, val_cr5);
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+ regmap_write(sai->regmap, FSL_SAI_TMR,
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+ ~0UL - ((1 << channels) - 1));
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+ } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
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+ regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
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+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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+ val_cr4);
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+ regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
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+ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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+ FSL_SAI_CR5_FBT_MASK, val_cr5);
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+ regmap_write(sai->regmap, FSL_SAI_RMR,
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+ ~0UL - ((1 << channels) - 1));
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+ }
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+ }
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+
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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val_cr4);
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