290 lines
12 KiB
C
290 lines
12 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_ptm_fw_regs_vdsl.h
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** PROJECT : UEIP
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** MODULES : PTM
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**
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** DATE : 7 Jul 2009
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** AUTHOR : Xu Liang
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** DESCRIPTION : PTM driver header file (firmware register for VDSL)
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 07 JUL 2009 Xu Liang Init Version
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*******************************************************************************/
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#ifndef IFXMIPS_PTM_FW_REGS_VDSL_H
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#define IFXMIPS_PTM_FW_REGS_VDSL_H
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#if defined(CONFIG_DANUBE)
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#error Danube is not VDSL PTM mode!
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#elif defined(CONFIG_AMAZON_SE)
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#error Amazon-SE is not VDSL PTM mode!
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#elif defined(CONFIG_AR9)
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#error AR9 is not VDSL PTM mode!
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#elif defined(CONFIG_VR9)
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#include "ifxmips_ptm_fw_regs_vr9.h"
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#else
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#error Platform is not specified!
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#endif
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/*
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* MIB Table Maintained by Firmware
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*/
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struct wan_rx_mib_table {
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unsigned int res1[2];
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unsigned int wrx_dropdes_pdu;
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unsigned int wrx_total_bytes;
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unsigned int res2[4];
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// wrx_total_pdu is implemented with hardware counter (not used by PTM TC)
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// check register "TC_RX_MIB_CMD"
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// "HEC_INC" used to increase preemption Gamma interface (wrx_total_pdu)
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// "AIIDLE_INC" used to increase normal Gamma interface (wrx_total_pdu)
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};
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struct wan_tx_mib_table {
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//unsigned int wtx_total_pdu; // version before 0.26
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//unsigned int small_pkt_drop_cnt;
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//unsigned int total_pkt_drop_cnt;
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unsigned int wrx_total_pdu; // version 0.26 and onwards
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unsigned int wrx_total_bytes;
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unsigned int wtx_total_pdu;
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unsigned int wtx_total_bytes;
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unsigned int wtx_cpu_dropsmall_pdu;
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unsigned int wtx_cpu_dropdes_pdu;
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unsigned int wtx_fast_dropsmall_pdu;
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unsigned int wtx_fast_dropdes_pdu;
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};
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/*
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* Host-PPE Communication Data Structure
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*/
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#if defined(__BIG_ENDIAN)
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struct fw_ver_id_new { // @2000
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/* 0 - 3h */
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unsigned int family :4;
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unsigned int package :4;
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unsigned int major :8;
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unsigned int middle :8;
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unsigned int minor :8;
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/* 4 - 7h */
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unsigned int features :32;
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};
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struct fw_ver_id { // @2001
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unsigned int family :4;
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unsigned int fwtype :4;
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unsigned int interface :4;
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unsigned int fwmode :4;
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unsigned int major :8;
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unsigned int minor :8;
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};
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struct cfg_std_data_len {
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unsigned int res1 :14;
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unsigned int byte_off :2; // byte offset in RX DMA channel
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unsigned int data_len :16; // data length for standard size packet buffer
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};
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struct tx_qos_cfg {
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unsigned int time_tick :16; // number of PP32 cycles per basic time tick
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unsigned int overhd_bytes :8; // number of overhead bytes per packet in rate shaping
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unsigned int eth1_eg_qnum :4; // number of egress QoS queues (< 8);
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unsigned int eth1_burst_chk :1; // always 1, more accurate WFQ
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unsigned int eth1_qss :1; // 1: FW QoS, 0: HW QoS
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unsigned int shape_en :1; // 1: enable rate shaping, 0: disable
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unsigned int wfq_en :1; // 1: WFQ enabled, 0: strict priority enabled
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};
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struct psave_cfg {
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unsigned int res1 :15;
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unsigned int start_state :1; // 1: start from partial PPE reset, 0: start from full PPE reset
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unsigned int res2 :15;
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unsigned int sleep_en :1; // 1: enable sleep mode, 0: disable sleep mode
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};
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struct eg_bwctrl_cfg {
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unsigned int fdesc_wm :16; // if free descriptors in QoS/Swap channel is less than this watermark, large size packets are discarded
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unsigned int class_len :16; // if packet length is not less than this value, the packet is recognized as large packet
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};
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struct test_mode {
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unsigned int res1 :30;
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unsigned int mib_clear_mode :1; // 1: MIB counter is cleared with TPS-TC software reset, 0: MIB counter not cleared
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unsigned int test_mode :1; // 1: test mode, 0: normal mode
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};
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struct gpio_mode {
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unsigned int res1 :3;
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unsigned int gpio_bit_bc1 :5;
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unsigned int res2 :3;
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unsigned int gpio_bit_bc0 :5;
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unsigned int res3 :7;
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unsigned int gpio_bc1_en :1;
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unsigned int res4 :7;
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unsigned int gpio_bc0_en :1;
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};
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struct gpio_wm_cfg {
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unsigned int stop_wm_bc1 :8;
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unsigned int start_wm_bc1 :8;
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unsigned int stop_wm_bc0 :8;
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unsigned int start_wm_bc0 :8;
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};
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struct rx_bc_cfg {
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unsigned int res1 :14;
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unsigned int local_state :2; // 0: local receiver is "Looking", 1: local receiver is "Freewheel Sync False", 2: local receiver is "Synced", 3: local receiver is "Freewheel Sync Truee"
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unsigned int res2 :15;
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unsigned int remote_state :1; // 0: remote receiver is "Out-of-Sync", 1: remote receiver is "Synced"
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unsigned int to_false_th :16; // the number of consecutive "Miss Sync" for leaving "Freewheel Sync False" to "Looking" (default 3)
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unsigned int to_looking_th :16; // the number of consecutive "Miss Sync" for leaving "Freewheel Sync True" to "Freewheel Sync False" (default 7)
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unsigned int res_word[30];
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};
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struct rx_gamma_itf_cfg {
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unsigned int res1 :31;
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unsigned int receive_state :1; // 0: "Out-of-Fragment", 1: "In-Fragment"
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unsigned int res2 :16;
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unsigned int rx_min_len :8; // min length of packet, padding if packet length is smaller than this value
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unsigned int rx_pad_en :1; // 0: padding disabled, 1: padding enabled
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unsigned int res3 :2;
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unsigned int rx_eth_fcs_ver_dis :1; // 0: ETH FCS verification is enabled, 1: disabled
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unsigned int rx_rm_eth_fcs :1; // 0: ETH FCS field is not removed, 1: ETH FCS field is removed
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unsigned int rx_tc_crc_ver_dis :1; // 0: TC CRC verification enabled, 1: disabled
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unsigned int rx_tc_crc_size :2; // 0: 0-bit, 1: 16-bit, 2: 32-bit
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unsigned int rx_eth_fcs_result; // if the ETH FCS result matches this magic number, then the packet is valid packet
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unsigned int rx_tc_crc_result; // if the TC CRC result matches this magic number, then the packet is valid packet
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unsigned int rx_crc_cfg :16; // TC CRC config, please check the description of SAR context data structure in the hardware spec
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unsigned int res4 :16;
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unsigned int rx_eth_fcs_init_value; // ETH FCS initialization value
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unsigned int rx_tc_crc_init_value; // TC CRC initialization value
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unsigned int res_word1;
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unsigned int rx_max_len_sel :1; // 0: normal, the max length is given by MAX_LEN_NORMAL, 1: fragment, the max length is given by MAX_LEN_FRAG
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unsigned int res5 :2;
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unsigned int rx_edit_num2 :4; // number of bytes to be inserted/removed
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unsigned int rx_edit_pos2 :7; // first byte position to be edited
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unsigned int rx_edit_type2 :1; // 0: remove, 1: insert
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unsigned int rx_edit_en2 :1; // 0: disable insertion or removal of data, 1: enable
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unsigned int res6 :3;
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unsigned int rx_edit_num1 :4; // number of bytes to be inserted/removed
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unsigned int rx_edit_pos1 :7; // first byte position to be edited
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unsigned int rx_edit_type1 :1; // 0: remove, 1: insert
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unsigned int rx_edit_en1 :1; // 0: disable insertion or removal of data, 1: enable
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unsigned int res_word2[2];
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unsigned int rx_inserted_bytes_1l;
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unsigned int rx_inserted_bytes_1h;
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unsigned int rx_inserted_bytes_2l;
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unsigned int rx_inserted_bytes_2h;
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int rx_len_adj; // the packet length adjustment, it is sign integer
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unsigned int res_word3[16];
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};
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struct tx_bc_cfg {
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unsigned int fill_wm :16; // default 2
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unsigned int uflw_wm :16; // default 2
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unsigned int res_word[31];
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};
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struct tx_gamma_itf_cfg {
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unsigned int res_word1;
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unsigned int res1 :8;
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unsigned int tx_len_adj :4; // 4 * (not TX_ETH_FCS_GEN_DIS) + TX_TC_CRC_SIZE
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unsigned int tx_crc_off_adj :4; // 4 + TX_TC_CRC_SIZE
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unsigned int tx_min_len :8; // min length of packet, if length is less than this value, packet is padded
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unsigned int res2 :3;
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unsigned int tx_eth_fcs_gen_dis :1; // 0: ETH FCS generation enabled, 1: disabled
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unsigned int res3 :2;
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unsigned int tx_tc_crc_size :2; // 0: 0-bit, 1: 16-bit, 2: 32-bit
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unsigned int res4 :24;
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unsigned int queue_mapping :8; // TX queue attached to this Gamma interface
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unsigned int res_word2;
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unsigned int tx_crc_cfg :16; // TC CRC config, please check the description of SAR context data structure in the hardware spec
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unsigned int res5 :16;
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unsigned int tx_eth_fcs_init_value; // ETH FCS initialization value
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unsigned int tx_tc_crc_init_value; // TC CRC initialization value
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unsigned int res_word3[25];
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};
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struct wtx_qos_q_desc_cfg {
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unsigned int threshold :8;
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unsigned int length :8;
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unsigned int addr :16;
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unsigned int rd_ptr :16;
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unsigned int wr_ptr :16;
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};
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struct wtx_eg_q_shaping_cfg {
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unsigned int t :8;
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unsigned int w :24;
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unsigned int s :16;
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unsigned int r :16;
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unsigned int res1 :8;
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unsigned int d :24; // ppe internal variable
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unsigned int res2 :8;
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unsigned int tick_cnt :8; // ppe internal variable
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unsigned int b :16; // ppe internal variable
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};
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/* DMA descriptor */
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struct rx_descriptor {
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/* 0 - 3h */
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unsigned int own :1; // 0: Central DMA TX or MIPS, 1: PPE
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unsigned int c :1; // PPE tells current descriptor is complete
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int res1 :3;
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unsigned int byteoff :2;
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unsigned int res2 :7;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int res3 :4;
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unsigned int dataptr :28; // byte address
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};
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struct tx_descriptor {
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/* 0 - 3h */
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unsigned int own :1; // CPU path - 0: MIPS, 1: PPE Dispatcher, Fastpath - 0: PPE Dispatcher, 1: Central DMA, QoS Queue - 0: PPE Dispatcher, 1: PPE DMA, SWAP Channel - 0: MIPS, 1: PPE Dispatcher
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unsigned int c :1; // MIPS or central DMA tells PPE the current descriptor is complete
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unsigned int sop :1;
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unsigned int eop :1;
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unsigned int byteoff :5;
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unsigned int qid :4; // TX Queue ID, bit 3 is reserved
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unsigned int res1 :3;
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unsigned int datalen :16;
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/* 4 - 7h */
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unsigned int small :1; // 0: standard size, 1: less than standard size
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unsigned int res2 :3;
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unsigned int dataptr :28; // byte address
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};
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#else /* defined(__BIG_ENDIAN) */
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#error structures are defined in big endian
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#endif /* defined(__BIG_ENDIAN) */
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#endif // IFXMIPS_PTM_FW_REGS_VDSL_H
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