72 lines
2.0 KiB
Diff
72 lines
2.0 KiB
Diff
From 007ad475ba7f0d5d4d3e43a06e46a8a46d31c9d2 Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:29:51 +0530
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Subject: [PATCH] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from
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PLL clocks
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
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on the request from dependent clocks. Doing so will result in the
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unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
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clocks.
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Cc: stable@vger.kernel.org
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Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 6 ------
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1 file changed, 6 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -76,7 +76,6 @@ static struct clk_fixed_factor gpll0_out
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&gpll0_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -122,7 +121,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll2_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -155,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll4_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -189,7 +186,6 @@ static struct clk_alpha_pll_postdiv gpll
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&gpll6_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -202,7 +198,6 @@ static struct clk_fixed_factor gpll6_out
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&gpll6_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -267,7 +262,6 @@ static struct clk_alpha_pll_postdiv nss_
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&nss_crypto_pll_main.clkr.hw },
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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- .flags = CLK_SET_RATE_PARENT,
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},
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};
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