38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
From d04c74e3f30be64b0e14d7ed2b6088f91ac6ea64 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 16 Mar 2022 16:44:45 +0100
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Subject: [PATCH] drm/vc4: plane: Prevent async update if we don't have
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a dlist
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The vc4 planes are setup in hardware by creating a hardware descriptor
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in a dedicated RAM. As part of the process to setup a plane in KMS, we
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thus need to allocate some part of that dedicated RAM to store our
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descriptor there.
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The async update path will just reuse the descriptor already allocated
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for that plane and will modify it directly in RAM to match whatever has
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been asked for.
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In order to do that, it will compare the descriptor for the old plane
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state and the new plane state, will make sure they fit in the same size,
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and check that only the position or buffer address have changed.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -1429,6 +1429,10 @@ static int vc4_plane_atomic_async_check(
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old_vc4_state = to_vc4_plane_state(plane->state);
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new_vc4_state = to_vc4_plane_state(new_plane_state);
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+
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+ if (!new_vc4_state->hw_dlist)
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+ return -EINVAL;
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+
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if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
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old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
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old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
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