67 lines
2.4 KiB
Diff
67 lines
2.4 KiB
Diff
From 66d8a98666f29d7f8de926963bd4965aeeb89f13 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 8 Nov 2021 17:32:45 +0000
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Subject: [PATCH] drm/vc4: Enable gamma block only when required.
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With HVS5 the gamma block is now only reprogrammed with
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a disable/enable. Loading the table from vc4_hvs_init_channel
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(called from vc4_hvs_atomic_enable) appears to be at an
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invalid point in time and so isn't applied.
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Switch to enabling and disabling the gamma table instead. This
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isn't safe if the pipeline is running, but it isn't now.
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For HVS4 it is safe to enable and disable dynamically, so
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adopt that approach there too.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 22 +++++++++++++++++-----
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1 file changed, 17 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -503,8 +503,12 @@ static int vc4_hvs_init_channel(struct v
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dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
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dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
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+ if (crtc->state->gamma_lut)
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+ /* Enable gamma on if required */
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+ dispbkgndx |= SCALER_DISPBKGND_GAMMA;
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+
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HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
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- SCALER_DISPBKGND_AUTOHS | SCALER_DISPBKGND_GAMMA |
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+ SCALER_DISPBKGND_AUTOHS |
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(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
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/* Reload the LUT, since the SRAMs would have been disabled if
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@@ -741,17 +745,25 @@ void vc4_hvs_atomic_flush(struct drm_crt
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u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
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if (crtc->state->gamma_lut) {
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- if (!vc4->hvs->hvs5)
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+ if (!vc4->hvs->hvs5) {
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vc4_hvs_update_gamma_lut(crtc);
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- else
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+ dispbkgndx |= SCALER_DISPBKGND_GAMMA;
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+ } else {
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vc5_hvs_update_gamma_lut(crtc);
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- dispbkgndx |= SCALER_DISPBKGND_GAMMA;
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+ }
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} else {
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/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
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* in hardware, which is the same as a linear lut that
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* DRM expects us to use in absence of a user lut.
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+ *
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+ * Do NOT change state dynamically for hvs5 as it
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+ * inserts a delay in the pipeline that will cause
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+ * stalls if enabled/disabled whilst running. The other
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+ * should already be disabling/enabling the pipeline
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+ * when gamma changes.
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*/
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- dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
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+ if (!vc4->hvs->hvs5)
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+ dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
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}
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
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}
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