159 lines
5.1 KiB
Diff
159 lines
5.1 KiB
Diff
From 81fe25670ae332380379026469c272e5d466c4cb Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 15 Dec 2021 10:17:39 +0100
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Subject: [PATCH] drm/vc4: plane: Add support for YUV color encodings
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and ranges
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The BT601/BT709 color encoding and limited vs full
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range properties were not being exposed, defaulting
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always to BT601 limited range.
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Expose the parameters and set the registers appropriately.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
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Link: https://lore.kernel.org/r/20211215091739.135042-4-maxime@cerno.tech
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 71 +++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 19 ++++++---
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2 files changed, 82 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -619,6 +619,51 @@ static int vc4_plane_allocate_lbm(struct
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return 0;
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}
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+/*
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+ * The colorspace conversion matrices are held in 3 entries in the dlist.
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+ * Create an array of them, with entries for each full and limited mode, and
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+ * each supported colorspace.
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+ */
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+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
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+ {
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+ /* Limited range */
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+ {
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+ /* BT601 */
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+ SCALER_CSC0_ITR_R_601_5,
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+ SCALER_CSC1_ITR_R_601_5,
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+ SCALER_CSC2_ITR_R_601_5,
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+ }, {
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+ /* BT709 */
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+ SCALER_CSC0_ITR_R_709_3,
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+ SCALER_CSC1_ITR_R_709_3,
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+ SCALER_CSC2_ITR_R_709_3,
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+ }, {
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+ /* BT2020 */
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+ SCALER_CSC0_ITR_R_2020,
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+ SCALER_CSC1_ITR_R_2020,
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+ SCALER_CSC2_ITR_R_2020,
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+ }
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+ }, {
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+ /* Full range */
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+ {
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+ /* JFIF */
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+ SCALER_CSC0_JPEG_JFIF,
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+ SCALER_CSC1_JPEG_JFIF,
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+ SCALER_CSC2_JPEG_JFIF,
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+ }, {
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+ /* BT709 */
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+ SCALER_CSC0_ITR_R_709_3_FR,
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+ SCALER_CSC1_ITR_R_709_3_FR,
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+ SCALER_CSC2_ITR_R_709_3_FR,
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+ }, {
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+ /* BT2020 */
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+ SCALER_CSC0_ITR_R_2020_FR,
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+ SCALER_CSC1_ITR_R_2020_FR,
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+ SCALER_CSC2_ITR_R_2020_FR,
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+ }
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+ }
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+};
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+
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/* Writes out a full display list for an active plane to the plane's
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* private dlist state.
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*/
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@@ -1013,9 +1058,20 @@ static int vc4_plane_mode_set(struct drm
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/* Colorspace conversion words */
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if (vc4_state->is_yuv) {
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- vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
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- vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
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- vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
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+ enum drm_color_encoding color_encoding = state->color_encoding;
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+ enum drm_color_range color_range = state->color_range;
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+ const u32 *ccm;
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+
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+ if (color_encoding >= DRM_COLOR_ENCODING_MAX)
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+ color_encoding = DRM_COLOR_YCBCR_BT601;
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+ if (color_range >= DRM_COLOR_RANGE_MAX)
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+ color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
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+
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+ ccm = colorspace_coeffs[color_range][color_encoding];
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+
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+ vc4_dlist_write(vc4_state, ccm[0]);
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+ vc4_dlist_write(vc4_state, ccm[1]);
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+ vc4_dlist_write(vc4_state, ccm[2]);
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}
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vc4_state->lbm_offset = 0;
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@@ -1444,6 +1500,15 @@ struct drm_plane *vc4_plane_init(struct
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DRM_MODE_REFLECT_X |
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DRM_MODE_REFLECT_Y);
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+ drm_plane_create_color_properties(plane,
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+ BIT(DRM_COLOR_YCBCR_BT601) |
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+ BIT(DRM_COLOR_YCBCR_BT709) |
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+ BIT(DRM_COLOR_YCBCR_BT2020),
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+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
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+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
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+ DRM_COLOR_YCBCR_BT709,
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+ DRM_COLOR_YCBCR_LIMITED_RANGE);
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+
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return plane;
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}
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -983,7 +983,10 @@ enum hvs_pixel_format {
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#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
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#define SCALER_CSC0_ITR_R_601_5 0x00f00000
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#define SCALER_CSC0_ITR_R_709_3 0x00f00000
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+#define SCALER_CSC0_ITR_R_2020 0x00f00000
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#define SCALER_CSC0_JPEG_JFIF 0x00000000
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+#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
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+#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
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/* S2.8 contribution of Cb to Green */
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#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
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@@ -998,8 +1001,11 @@ enum hvs_pixel_format {
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#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
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#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
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#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
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-#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
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-#define SCALER_CSC1_JPEG_JFIF 0xea34a400
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+#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
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+#define SCALER_CSC1_ITR_R_2020 0xf43594a8
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+#define SCALER_CSC1_JPEG_JFIF 0xea349400
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+#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
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+#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
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/* S2.8 contribution of Cb to Red */
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#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
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@@ -1010,9 +1016,12 @@ enum hvs_pixel_format {
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/* S2.8 contribution of Cb to Blue */
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#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
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#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
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-#define SCALER_CSC2_ITR_R_601_5 0x00066204
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-#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
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-#define SCALER_CSC2_JPEG_JFIF 0x000599c5
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+#define SCALER_CSC2_ITR_R_601_5 0x00066604
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+#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
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+#define SCALER_CSC2_ITR_R_2020 0x0006b624
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+#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
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+#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
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+#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
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#define SCALER_TPZ0_VERT_RECALC BIT(31)
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#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
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