80 lines
3.0 KiB
Diff
80 lines
3.0 KiB
Diff
From 7d8f187f47cd5583c3c04b3dfb281c738443198a Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Thu, 11 Jun 2020 09:57:03 +0100
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Subject: [PATCH] PCI: brcmstb: Add DT property to control L1SS
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The BRCM PCIe block has controls to enable control of the CLKREQ#
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signal by the L1SS, and to gate the refclk with the CLKREQ# input.
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These controls are mutually exclusive - the upstream code sets the
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latter, but some use cases require the former.
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Add a Device Tree property - brcm,enable-l1ss - to switch to the
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L1SS configuration.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 30 ++++++++++++++++++++-------
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1 file changed, 23 insertions(+), 7 deletions(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -116,8 +116,9 @@
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
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-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK BIT(1)
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK BIT(21)
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK BIT(27)
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#define PCIE_INTR2_CPU_BASE 0x4300
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@@ -283,6 +284,7 @@ struct brcm_pcie {
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struct clk *clk;
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struct device_node *np;
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bool ssc;
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+ bool l1ss;
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int gen;
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u64 msi_target_addr;
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struct brcm_msi *msi;
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@@ -1033,12 +1035,25 @@ static int brcm_pcie_setup(struct brcm_p
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
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writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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- /*
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- * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
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- * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
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- */
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tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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- tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
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+ if (pcie->l1ss) {
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+ /*
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+ * Enable CLKREQ# signalling include L1 Substate control of
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+ * the CLKREQ# signal and the external reference clock buffer.
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+ * meet requirement for Endpoints that require CLKREQ#
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+ * assertion to clock active within 400ns.
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+ */
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+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
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+ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
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+ } else {
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+ /*
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+ * Refclk from RC should be gated with CLKREQ# input when
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+ * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
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+ * field to 1.
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+ */
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+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
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+ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
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+ }
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writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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return 0;
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@@ -1267,6 +1282,7 @@ static int brcm_pcie_probe(struct platfo
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pcie->gen = (ret < 0) ? 0 : ret;
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pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
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+ pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
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ret = clk_prepare_enable(pcie->clk);
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if (ret) {
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