mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-06-19 23:28:29 +02:00
Adrian Schmutzler
e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
151 lines
2.3 KiB
Plaintext
151 lines
2.3 KiB
Plaintext
/dts-v1/;
|
|
|
|
#include "mt7621.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "mtc,wr1201", "mediatek,mt7621-soc";
|
|
model = "MTC Wireless Router WR1201";
|
|
|
|
aliases {
|
|
led-boot = &led_power;
|
|
led-failsafe = &led_power;
|
|
led-running = &led_power;
|
|
led-upgrade = &led_power;
|
|
label-mac-device = ðernet;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,57600";
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_power: power {
|
|
label = "wr1201:green:power";
|
|
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
usb {
|
|
label = "wr1201:green:usb";
|
|
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
|
|
trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
|
|
linux,default-trigger = "usbport";
|
|
};
|
|
|
|
eth_link {
|
|
label = "wr1201:green:eth_link";
|
|
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wps {
|
|
label = "wr1201:green:wps";
|
|
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <10000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "Bootloader";
|
|
reg = <0x0 0x30000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
label = "Config";
|
|
reg = <0x30000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
factory: partition@40000 {
|
|
label = "factory";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x50000 0xfa0000>;
|
|
};
|
|
|
|
partition@ff0000 {
|
|
label = "Second_Config";
|
|
reg = <0xff0000 0x10000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ðernet {
|
|
mtd-mac-address = <&factory 0x4>;
|
|
};
|
|
|
|
&sdhci {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
wifi@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x8000>;
|
|
ieee80211-freq-limit = <5000000 6000000>;
|
|
|
|
led {
|
|
led-sources = <2>;
|
|
led-active-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie1 {
|
|
wifi@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x0000>;
|
|
ieee80211-freq-limit = <2400000 2500000>;
|
|
|
|
led {
|
|
led-sources = <2>;
|
|
led-active-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
&state_default {
|
|
gpio {
|
|
ralink,group = "rgmii2";
|
|
ralink,function = "gpio";
|
|
};
|
|
};
|