49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 611e2dabb4b3243d176739fd6a5a34d007fa3f86 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 14 Mar 2023 00:34:26 +0000
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Subject: [PATCH 1/2] net: ethernet: mtk_eth_soc: reset PCS state
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Reset the internal PCS state machine when changing interface mode.
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This prevents confusing the state machine when changing interface
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modes, e.g. from SGMII to 2500Base-X or vice-versa.
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Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
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Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Tested-by: Bjørn Mork <bjorn@mork.no>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++++
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2 files changed, 8 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -542,6 +542,10 @@
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#define SGMII_SEND_AN_ERROR_EN BIT(11)
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#define SGMII_IF_MODE_MASK GENMASK(5, 1)
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+/* Register to reset SGMII design */
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+#define SGMII_RESERVED_0 0x34
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+#define SGMII_SW_RESET BIT(0)
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+
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/* Register to set SGMII speed, ANA RG_ Control Signals III*/
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#define SGMSYS_ANA_RG_CS3 0x2028
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#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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+ /* Reset SGMII PCS state */
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+ regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
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+ SGMII_SW_RESET, SGMII_SW_RESET);
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+
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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rgc3 = RG_PHY_SPEED_3_125G;
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else
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