56 lines
2.2 KiB
Diff
56 lines
2.2 KiB
Diff
From b25aac1f55c29048e5a6ab24ab0e2aea12cb4887 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 20 Mar 2024 00:47:58 +0100
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Subject: [PATCH] mtd: rawnand: qcom: Fix broken misc_cmd_type in exec_op
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misc_cmd_type in exec_op have multiple problems. With commit a82990c8a409
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("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") it was
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reworked and generalized but actually dropped the handling of the
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RESET_DEVICE command.
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The rework itself was correct with supporting case where a single misc
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command is handled, but became problematic by the addition of exiting
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early if we didn't had an ERASE or an OP_PROGRAM_PAGE operation.
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Also additional logic was added without clear explaination causing the
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erase command to be broken on testing it on a ipq806x nandc.
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Add some additional logic to restore RESET_DEVICE command handling and
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fix erase command.
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Fixes: a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path")
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Cc: stable@vger.kernel.org
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 7 +++----
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1 file changed, 3 insertions(+), 4 deletions(-)
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diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
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index b079605c84d3..b8cff9240b28 100644
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
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host->cfg0_raw & ~(7 << CW_PER_PAGE));
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nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
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instrs = 3;
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- } else {
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+ } else if (q_op.cmd_reg != OP_RESET_DEVICE) {
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return 0;
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}
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@@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
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nandc_set_reg(chip, NAND_EXEC_CMD, 1);
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write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
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- (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
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- 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
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- NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
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+ if (q_op.cmd_reg == OP_BLOCK_ERASE)
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+ write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
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write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
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read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
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--
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2.43.0
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