56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From 7bbbfef1c98e832cbd55e66ac2d7f13ec0a2b11e Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 21 Feb 2020 14:34:31 +0100
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Subject: [PATCH] drm/vc4: crtc: Enable and disable the PV in
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atomic_enable / disable
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The VIDEN bit in the pixelvalve currently being used to enable or disable
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the pixelvalve seems to not be enough in some situations, which whill end
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up with the pixelvalve stalling.
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In such a case, even re-enabling VIDEN doesn't bring it back and we need to
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clear the FIFO. This can only be done if the pixelvalve is disabled though.
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In order to overcome this, we can configure the pixelvalve during
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mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO
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there, and in atomic_disable disable the pixelvalve again.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++++---
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1 file changed, 7 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -374,9 +374,7 @@ static void vc4_crtc_config_pv(struct dr
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PV_CONTROL_TRIGGER_UNDERFLOW |
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PV_CONTROL_WAIT_HSTART |
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VC4_SET_FIELD(vc4_encoder->clock_select,
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- PV_CONTROL_CLK_SELECT) |
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- PV_CONTROL_FIFO_CLR |
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- PV_CONTROL_EN);
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+ PV_CONTROL_CLK_SELECT));
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}
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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@@ -467,6 +465,8 @@ static void vc4_crtc_atomic_disable(stru
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ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
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WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
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+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
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+
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if (HVS_READ(SCALER_DISPCTRLX(chan)) &
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SCALER_DISPCTRLX_ENABLE) {
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HVS_WRITE(SCALER_DISPCTRLX(chan),
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@@ -554,6 +554,10 @@ static void vc4_crtc_atomic_enable(struc
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require_hvs_enabled(dev);
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+ /* Reset the PV fifo. */
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+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |
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+ PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
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+
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/* Enable vblank irq handling before crtc is started otherwise
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* drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
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*/
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