70 lines
2.5 KiB
Diff
70 lines
2.5 KiB
Diff
--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -196,7 +196,7 @@ struct flash_info {
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u16 page_size;
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u16 addr_width;
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- u16 flags;
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+ u32 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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@@ -233,6 +233,10 @@ struct flash_info {
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
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+#define SPI_NOR_4BIT_BP BIT(17) /*
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+ * Flash SR has 4 bit fields (BP0-3)
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+ * for block protection.
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+ */
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/* Part specific fixup hooks. */
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const struct spi_nor_fixups *fixups;
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@@ -1987,6 +1991,9 @@ static int spi_nor_clear_sr_bp(struct sp
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int ret;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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+ if (nor->flags & SNOR_F_HAS_4BIT_BP)
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+ mask |= SR_BP3;
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+
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ret = read_sr(nor);
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if (ret < 0) {
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dev_err(nor->dev, "error while reading status register\n");
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@@ -2340,7 +2347,7 @@ static const struct flash_info spi_nor_i
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{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
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{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
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{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
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- { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
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+ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_4BIT_BP) },
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{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
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{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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@@ -5028,6 +5035,9 @@ int spi_nor_scan(struct spi_nor *nor, co
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if (info->flags & USE_CLSR)
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nor->flags |= SNOR_F_USE_CLSR;
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+ if (info->flags & SPI_NOR_4BIT_BP)
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+ nor->flags |= SNOR_F_HAS_4BIT_BP;
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+
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if (info->flags & SPI_NOR_NO_ERASE)
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mtd->flags |= MTD_NO_ERASE;
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -127,6 +127,7 @@
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#define SR_BP0 BIT(2) /* Block protect 0 */
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#define SR_BP1 BIT(3) /* Block protect 1 */
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#define SR_BP2 BIT(4) /* Block protect 2 */
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+#define SR_BP3 BIT(5) /* Block protect 3 */
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#define SR_TB BIT(5) /* Top/Bottom protect */
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#define SR_SRWD BIT(7) /* SR write protect */
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/* Spansion/Cypress specific status bits */
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@@ -243,6 +244,7 @@ enum spi_nor_option_flags {
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SNOR_F_4B_OPCODES = BIT(6),
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SNOR_F_HAS_4BAIT = BIT(7),
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SNOR_F_HAS_LOCK = BIT(8),
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+ SNOR_F_HAS_4BIT_BP = BIT(12),
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};
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/**
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