48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From 2b0fe9137aa32d7fc367bf3a1cef4fa97ece6d58 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 23 Aug 2022 22:43:51 +0200
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Subject: [PATCH] phy: qcom-qmp-pcie: make pipe clock rate configurable
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IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
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like every other PCIe QMP PHY does, so make it configurable as part of the
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qmp_phy_cfg.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
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+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
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@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
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/* true, if PHY has secondary tx/rx lanes to be configured */
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bool is_dual_lane_phy;
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+ /* QMP PHY pipe clock interface rate */
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+ unsigned long pipe_clock_rate;
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+
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/* true, if PCS block has no separate SW_RESET register */
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bool no_pcs_sw_reset;
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};
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@@ -5139,8 +5142,15 @@ static int phy_pipe_clk_register(struct
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init.ops = &clk_fixed_rate_ops;
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- /* controllers using QMP phys use 125MHz pipe clock interface */
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- fixed->fixed_rate = 125000000;
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+ /*
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+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
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+ * unless other frequency is specified in the PHY config.
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+ */
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+ if (qmp->phys[0]->cfg->pipe_clock_rate)
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+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
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+ else
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+ fixed->fixed_rate = 125000000;
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+
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fixed->hw.init = &init;
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ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
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