239 lines
7.1 KiB
Diff
239 lines
7.1 KiB
Diff
From 876f8ef32ec09fb566cc6ecdf4c96a8348f135b6 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 18 Jan 2017 07:31:56 +1100
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Subject: [PATCH] clk: bcm2835: Register the DSI0/DSI1 pixel clocks.
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The DSI pixel clocks are muxed from clocks generated in the analog phy
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by the DSI driver. In order to set them as parents, we need to do the
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same name lookup dance on them as we do for our root oscillator.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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(cherry picked from commit 8a39e9fa578229fd4604266c6ebb1a3a77d7994c)
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---
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.../bindings/clock/brcm,bcm2835-cprman.txt | 15 ++-
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drivers/clk/bcm/clk-bcm2835.c | 121 +++++++++++++++++++--
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include/dt-bindings/clock/bcm2835.h | 2 +
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3 files changed, 125 insertions(+), 13 deletions(-)
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--- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
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+++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
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@@ -16,7 +16,20 @@ Required properties:
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- #clock-cells: Should be <1>. The permitted clock-specifier values can be
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found in include/dt-bindings/clock/bcm2835.h
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- reg: Specifies base physical address and size of the registers
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-- clocks: The external oscillator clock phandle
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+- clocks: phandles to the parent clocks used as input to the module, in
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+ the following order:
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+
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+ - External oscillator
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+ - DSI0 byte clock
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+ - DSI0 DDR2 clock
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+ - DSI0 DDR clock
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+ - DSI1 byte clock
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+ - DSI1 DDR2 clock
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+ - DSI1 DDR clock
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+
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+ Only external oscillator is required. The DSI clocks may
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+ not be present, in which case their children will be
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+ unusable.
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Example:
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -297,11 +297,32 @@
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#define LOCK_TIMEOUT_NS 100000000
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#define BCM2835_MAX_FB_RATE 1750000000u
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+/*
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+ * Names of clocks used within the driver that need to be replaced
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+ * with an external parent's name. This array is in the order that
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+ * the clocks node in the DT references external clocks.
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+ */
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+static const char *const cprman_parent_names[] = {
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+ "xosc",
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+ "dsi0_byte",
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+ "dsi0_ddr2",
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+ "dsi0_ddr",
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+ "dsi1_byte",
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+ "dsi1_ddr2",
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+ "dsi1_ddr",
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+};
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+
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struct bcm2835_cprman {
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struct device *dev;
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void __iomem *regs;
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spinlock_t regs_lock; /* spinlock for all clocks */
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- const char *osc_name;
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+
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+ /*
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+ * Real names of cprman clock parents looked up through
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+ * of_clk_get_parent_name(), which will be used in the
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+ * parent_names[] arrays for clock registration.
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+ */
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+ const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
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/* Must be last */
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struct clk_hw_onecell_data onecell;
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@@ -913,6 +934,9 @@ static long bcm2835_clock_rate_from_divi
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const struct bcm2835_clock_data *data = clock->data;
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u64 temp;
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+ if (data->int_bits == 0 && data->frac_bits == 0)
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+ return parent_rate;
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+
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/*
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* The divisor is a 12.12 fixed point field, but only some of
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* the bits are populated in any given clock.
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@@ -936,7 +960,12 @@ static unsigned long bcm2835_clock_get_r
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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const struct bcm2835_clock_data *data = clock->data;
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- u32 div = cprman_read(cprman, data->div_reg);
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+ u32 div;
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+
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+ if (data->int_bits == 0 && data->frac_bits == 0)
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+ return parent_rate;
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+
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+ div = cprman_read(cprman, data->div_reg);
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return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
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}
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@@ -1215,7 +1244,7 @@ static struct clk_hw *bcm2835_register_p
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memset(&init, 0, sizeof(init));
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/* All of the PLLs derive from the external oscillator. */
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- init.parent_names = &cprman->osc_name;
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+ init.parent_names = &cprman->real_parent_names[0];
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init.num_parents = 1;
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init.name = data->name;
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init.ops = &bcm2835_pll_clk_ops;
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@@ -1303,18 +1332,22 @@ static struct clk_hw *bcm2835_register_c
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struct bcm2835_clock *clock;
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struct clk_init_data init;
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const char *parents[1 << CM_SRC_BITS];
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- size_t i;
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+ size_t i, j;
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int ret;
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/*
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- * Replace our "xosc" references with the oscillator's
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- * actual name.
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+ * Replace our strings referencing parent clocks with the
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+ * actual clock-output-name of the parent.
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*/
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for (i = 0; i < data->num_mux_parents; i++) {
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- if (strcmp(data->parents[i], "xosc") == 0)
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- parents[i] = cprman->osc_name;
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- else
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- parents[i] = data->parents[i];
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+ parents[i] = data->parents[i];
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+
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+ for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) {
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+ if (strcmp(parents[i], cprman_parent_names[j]) == 0) {
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+ parents[i] = cprman->real_parent_names[j];
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+ break;
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+ }
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+ }
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}
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memset(&init, 0, sizeof(init));
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@@ -1450,6 +1483,47 @@ static const char *const bcm2835_clock_v
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__VA_ARGS__)
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/*
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+ * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
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+ * analog PHY. The _inv variants are generated internally to cprman,
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+ * but we don't use them so they aren't hooked up.
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+ */
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+static const char *const bcm2835_clock_dsi0_parents[] = {
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+ "gnd",
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+ "xosc",
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+ "testdebug0",
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+ "testdebug1",
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+ "dsi0_ddr",
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+ "dsi0_ddr_inv",
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+ "dsi0_ddr2",
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+ "dsi0_ddr2_inv",
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+ "dsi0_byte",
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+ "dsi0_byte_inv",
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+};
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+
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+static const char *const bcm2835_clock_dsi1_parents[] = {
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+ "gnd",
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+ "xosc",
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+ "testdebug0",
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+ "testdebug1",
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+ "dsi1_ddr",
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+ "dsi1_ddr_inv",
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+ "dsi1_ddr2",
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+ "dsi1_ddr2_inv",
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+ "dsi1_byte",
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+ "dsi1_byte_inv",
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+};
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+
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+#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \
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+ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
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+ .parents = bcm2835_clock_dsi0_parents, \
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+ __VA_ARGS__)
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+
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+#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
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+ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
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+ .parents = bcm2835_clock_dsi1_parents, \
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+ __VA_ARGS__)
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+
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+/*
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* the real definition of all the pll, pll_dividers and clocks
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* these make use of the above REGISTER_* macros
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*/
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@@ -1912,6 +1986,18 @@ static const struct bcm2835_clk_desc clk
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.div_reg = CM_DSI1EDIV,
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.int_bits = 4,
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.frac_bits = 8),
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+ [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
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+ .name = "dsi0p",
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+ .ctl_reg = CM_DSI0PCTL,
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+ .div_reg = CM_DSI0PDIV,
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+ .int_bits = 0,
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+ .frac_bits = 0),
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+ [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
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+ .name = "dsi1p",
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+ .ctl_reg = CM_DSI1PCTL,
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+ .div_reg = CM_DSI1PDIV,
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+ .int_bits = 0,
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+ .frac_bits = 0),
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/* the gates */
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@@ -1970,8 +2056,19 @@ static int bcm2835_clk_probe(struct plat
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if (IS_ERR(cprman->regs))
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return PTR_ERR(cprman->regs);
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- cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0);
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- if (!cprman->osc_name)
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+ memcpy(cprman->real_parent_names, cprman_parent_names,
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+ sizeof(cprman_parent_names));
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+ of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
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+ ARRAY_SIZE(cprman_parent_names));
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+
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+ /*
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+ * Make sure the external oscillator has been registered.
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+ *
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+ * The other (DSI) clocks are not present on older device
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+ * trees, which we still need to support for backwards
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+ * compatibility.
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+ */
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+ if (!cprman->real_parent_names[0])
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return -ENODEV;
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platform_set_drvdata(pdev, cprman);
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -64,3 +64,5 @@
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#define BCM2835_CLOCK_CAM1 46
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#define BCM2835_CLOCK_DSI0E 47
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#define BCM2835_CLOCK_DSI1E 48
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+#define BCM2835_CLOCK_DSI0P 49
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+#define BCM2835_CLOCK_DSI1P 50
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