100 lines
2.7 KiB
Diff
100 lines
2.7 KiB
Diff
From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Tue, 13 Apr 2021 12:57:15 +0200
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Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for
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additional modules
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Add register description for additional pipeline modules: the
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Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS)
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++
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1 file changed, 67 insertions(+)
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--- a/drivers/media/platform/atmel/atmel-isc-regs.h
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+++ b/drivers/media/platform/atmel/atmel-isc-regs.h
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@@ -90,6 +90,46 @@
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#define ISC_INT_DDONE BIT(8)
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#define ISC_INT_HISDONE BIT(12)
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+/* ISC DPC Control Register */
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+#define ISC_DPC_CTRL 0x40
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+
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+#define ISC_DPC_CTRL_DPCEN BIT(0)
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+#define ISC_DPC_CTRL_GDCEN BIT(1)
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+#define ISC_DPC_CTRL_BLCEN BIT(2)
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+
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+/* ISC DPC Config Register */
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+#define ISC_DPC_CFG 0x44
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+
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+#define ISC_DPC_CFG_BAYSEL_SHIFT 0
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+
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+#define ISC_DPC_CFG_EITPOL BIT(4)
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+
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+#define ISC_DPC_CFG_TA_ENABLE BIT(14)
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+#define ISC_DPC_CFG_TC_ENABLE BIT(13)
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+#define ISC_DPC_CFG_TM_ENABLE BIT(12)
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+
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+#define ISC_DPC_CFG_RE_MODE BIT(17)
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+
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+#define ISC_DPC_CFG_GDCCLP_SHIFT 20
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+#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20)
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+
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+#define ISC_DPC_CFG_BLOFF_SHIFT 24
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+#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24)
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+
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+#define ISC_DPC_CFG_BAYCFG_SHIFT 0
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+#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0)
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+/* ISC DPC Threshold Median Register */
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+#define ISC_DPC_THRESHM 0x48
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+
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+/* ISC DPC Threshold Closest Register */
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+#define ISC_DPC_THRESHC 0x4C
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+
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+/* ISC DPC Threshold Average Register */
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+#define ISC_DPC_THRESHA 0x50
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+
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+/* ISC DPC STatus Register */
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+#define ISC_DPC_SR 0x54
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+
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/* ISC White Balance Control Register */
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#define ISC_WB_CTRL 0x00000058
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@@ -153,6 +193,33 @@
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/* ISC_Gamma Correction Green Entry Register */
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#define ISC_GAM_RENTRY 0x00000298
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+/* ISC VHXS Control Register */
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+#define ISC_VHXS_CTRL 0x398
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+
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+/* ISC VHXS Source Size Register */
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+#define ISC_VHXS_SS 0x39C
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+
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+/* ISC VHXS Destination Size Register */
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+#define ISC_VHXS_DS 0x3A0
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+
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+/* ISC Vertical Factor Register */
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+#define ISC_VXS_FACT 0x3a4
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+
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+/* ISC Horizontal Factor Register */
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+#define ISC_HXS_FACT 0x3a8
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+
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+/* ISC Vertical Config Register */
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+#define ISC_VXS_CFG 0x3ac
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+
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+/* ISC Horizontal Config Register */
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+#define ISC_HXS_CFG 0x3b0
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+
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+/* ISC Vertical Tap Register */
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+#define ISC_VXS_TAP 0x3b4
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+
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+/* ISC Horizontal Tap Register */
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+#define ISC_HXS_TAP 0x434
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+
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/* Offset for CSC register specific to sama5d2 product */
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#define ISC_SAMA5D2_CSC_OFFSET 0
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