31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001
|
|
From: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Date: Thu, 19 Nov 2020 17:43:14 +0200
|
|
Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0
|
|
rate
|
|
|
|
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
|
|
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
|
|
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
|
|
The lower limit is changed to be able to set MCK0 accordingly by
|
|
DVFS.
|
|
|
|
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
|
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
---
|
|
drivers/clk/at91/sama7g5.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
--- a/drivers/clk/at91/sama7g5.c
|
|
+++ b/drivers/clk/at91/sama7g5.c
|
|
@@ -807,7 +807,7 @@ static const struct clk_pll_characterist
|
|
|
|
/* MCK0 characteristics. */
|
|
static const struct clk_master_characteristics mck0_characteristics = {
|
|
- .output = { .min = 140000000, .max = 200000000 },
|
|
+ .output = { .min = 50000000, .max = 200000000 },
|
|
.divisors = { 1, 2, 4, 3, 5 },
|
|
.have_div3_pres = 1,
|
|
};
|