88 lines
2.8 KiB
Diff
88 lines
2.8 KiB
Diff
From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001
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From: Aleksander Jan Bajkowski <olek2@wp.pl>
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Date: Wed, 21 Sep 2022 22:59:44 +0200
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Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE
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This patch is needed to handle interrupts by the second VPE on the Lantiq
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ARX100, xRX200, xRX300 and xRX330 SoCs. Switching some ICU interrupts to
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the second VPE results in a hang. Currently, the vsmp_init_secondary()
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function is responsible for enabling these interrupts. It only enables
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Malta-specific interrupts (SW0, SW1, HW4 and HW5).
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The MIPS core has 8 interrupts defined. On Lantiq SoCs, hardware
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interrupts are wired to an ICU instance. Each VPE has an independent
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instance of the ICU. The mapping of the ICU interrupts is shown below:
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SW0(IP0) - IPI call,
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SW1(IP1) - IPI resched,
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HW0(IP2) - ICU 0-31,
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HW1(IP3) - ICU 32-63,
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HW2(IP4) - ICU 64-95,
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HW3(IP5) - ICU 96-127,
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HW4(IP6) - ICU 128-159,
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HW5(IP7) - timer.
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This patch enables all interrupt lines on the second VPE.
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This problem affects multithreaded SoCs with a custom interrupt controller.
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SOCs with 1004Kc core and newer use the MIPS GIC. At this point, I am aware
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that the Realtek RTL839x and RTL930x SoCs may need a similar fix. In the
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future, this may be replaced with some generic solution.
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Tested on Lantiq xRX200.
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Suggested-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++--
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1 file changed, 24 insertions(+), 2 deletions(-)
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--- a/arch/mips/lantiq/prom.c
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+++ b/arch/mips/lantiq/prom.c
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@@ -31,6 +31,14 @@ static struct ltq_soc_info soc_info;
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/* for Multithreading (APRP), vpe.c will use it */
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unsigned long cp0_memsize;
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+/*
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+ * These structs are used to override vsmp_init_secondary()
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+ */
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+#if defined(CONFIG_MIPS_MT_SMP)
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+extern const struct plat_smp_ops vsmp_smp_ops;
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+static struct plat_smp_ops lantiq_smp_ops;
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+#endif
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+
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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@@ -87,6 +95,17 @@ void __init device_tree_init(void)
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unflatten_and_copy_device_tree();
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}
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+#if defined(CONFIG_MIPS_MT_SMP)
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+static void lantiq_init_secondary(void)
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+{
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+ /*
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+ * MIPS CPU startup function vsmp_init_secondary() will only
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+ * enable some of the interrupts for the second CPU/VPE.
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+ */
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+ set_c0_status(ST0_IM);
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+}
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+#endif
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+
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void __init prom_init(void)
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{
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/* call the soc specific detetcion code and get it to fill soc_info */
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@@ -98,7 +117,10 @@ void __init prom_init(void)
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prom_init_cmdline();
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#if defined(CONFIG_MIPS_MT_SMP)
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- if (register_vsmp_smp_ops())
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- panic("failed to register_vsmp_smp_ops()");
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+ if (cpu_has_mipsmt) {
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+ lantiq_smp_ops = vsmp_smp_ops;
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+ lantiq_smp_ops.init_secondary = lantiq_init_secondary;
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+ register_smp_ops(&lantiq_smp_ops);
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+ }
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#endif
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}
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