144 lines
5.3 KiB
Diff
144 lines
5.3 KiB
Diff
From patchwork Thu Sep 28 12:58:35 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,
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4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq
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mode
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819592
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Message-Id: <20170928125838.11887-5-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:35 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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The Aardvark has two interrupts sets:
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- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)
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- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)
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Only one set should be used, while another set should be masked.
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The second set, ISR1, is more advanced, the Legacy INT_X status bit is
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asserted once Assert_INTX message is received, and de-asserted after
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Deassert_INTX message is received. Therefore, it matches what the
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driver is currently doing in the ->irq_mask() and ->irq_unmask()
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functions. The ISR0 requires additional work to deassert the
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interrupt, which the driver doesn't do currently.
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This commit resolves a number of issues with legacy interrupts.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
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1 file changed, 24 insertions(+), 17 deletions(-)
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -105,7 +105,8 @@
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#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
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#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
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#define PCIE_ISR1_FLUSH BIT(5)
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-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
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+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
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+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
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#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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@@ -615,9 +616,9 @@ static void advk_pcie_irq_mask(struct ir
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static void advk_pcie_irq_unmask(struct irq_data *d)
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@@ -626,9 +627,9 @@ static void advk_pcie_irq_unmask(struct
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 mask;
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
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- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
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+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
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+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
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}
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static int advk_pcie_irq_map(struct irq_domain *h,
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@@ -771,29 +772,35 @@ static void advk_pcie_handle_msi(struct
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static void advk_pcie_handle_int(struct advk_pcie *pcie)
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{
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- u32 val, mask, status;
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+ u32 isr0_val, isr0_mask, isr0_status;
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+ u32 isr1_val, isr1_mask, isr1_status;
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int i, virq;
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- val = advk_readl(pcie, PCIE_ISR0_REG);
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- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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- status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
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-
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- if (!status) {
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- advk_writel(pcie, val, PCIE_ISR0_REG);
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+ isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
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+ isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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+ isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
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+
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+ isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
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+ isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
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+ isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
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+
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+ if (!isr0_status && !isr1_status) {
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+ advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
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+ advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
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return;
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}
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/* Process MSI interrupts */
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- if (status & PCIE_ISR0_MSI_INT_PENDING)
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+ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
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advk_pcie_handle_msi(pcie);
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/* Process legacy interrupts */
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for (i = 0; i < PCI_NUM_INTX; i++) {
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- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
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+ if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
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continue;
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- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
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- PCIE_ISR0_REG);
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+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
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+ PCIE_ISR1_REG);
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virq = irq_find_mapping(pcie->irq_domain, i);
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generic_handle_irq(virq);
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