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584d7c53bd
This commit introduces new subtarget for Marvell EBU Armada Cortex A53
processor based devices.
The first device is Globalscale ESPRESSObin. Some hardware specs:
SoC: Marvell Armada 3700LP (88F3720) dual core ARM Cortex A53
processor up to 1.2GHz
RAM: 512MB, 1GB or 2GB DDR3
Storage: SATA interface
µSD card slot with footprint for an optional 4GB EMMC
4MB SPI NOR flash for bootloader
Ethernet: Topaz Networking Switch (88E6341) with 3x GbE ports
Connectors: USB 3.0
USB 2.0
µUSB port connected to PL2303SA (USB to serial bridge
controller) for UART access
Expansion: 2x 46-pin GPIO headers for accessories and shields with
I2C, GPIOs, PWM, UART, SPI, MMC, etc
MiniPCIe slot
Misc: Reset button, JTAG interface
Currently booting only from µSD card is supported.
The boards depending on date of dispatch can come with various U-Boot
versions. For the newest version 2017.03-armada-17.10 no manual
intervention should be needed to boot OpenWrt image. For the older ones
it's necessary to modify default U-Boot environment:
1. Interrupt boot process to run U-Boot command line,
2. Run following commands:
(for version 2017.03-armada-17.06 and 2017.03-armada-17.08)
setenv bootcmd "load mmc 0:1 0x4d00000 boot.scr; source 0x4d00000"
saveenv
(for version 2015.01-armada-17.02 and 2015.01-armada-17.04)
setenv bootargs "console=ttyMV0,115200 root=/dev/mmcblk0p2 rw rootwait"
setenv bootcmd "ext4load mmc 0:1 ${fdt_addr} armada-3720-espressobin.dtb; ext4load mmc 0:1 ${kernel_addr} Image; booti ${kernel_addr} - ${fdt_addr}"
saveenv
3. Poweroff, insert SD card with OpenWrt image, boot and enjoy.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
54 lines
2.2 KiB
Diff
54 lines
2.2 KiB
Diff
From patchwork Thu Sep 28 12:58:33 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,
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2/7] PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819589
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Message-Id: <20170928125838.11887-3-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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stable@vger.kernel.org, Thomas Petazzoni
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<thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:33 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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When setting the PIO_ADDR_LS register during a configuration read, we
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were properly passing the device number, function number and register
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number, but not the bus number, causing issues when reading the
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configuration of PCIe devices.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Wilson Ding <dingwei@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -459,7 +459,7 @@ static int advk_pcie_rd_conf(struct pci_
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advk_writel(pcie, reg, PIO_CTRL);
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/* Program the address registers */
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- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
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+ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
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advk_writel(pcie, reg, PIO_ADDR_LS);
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advk_writel(pcie, 0, PIO_ADDR_MS);
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