255 lines
8.3 KiB
Diff
255 lines
8.3 KiB
Diff
From 25ce45fe40b574e5d7ffa407f7f2db03e7d5a910 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 22 Aug 2023 17:32:54 +0100
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Subject: [PATCH 112/250] net: ethernet: mtk_eth_soc: add support for in-SoC
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SRAM
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MT7981, MT7986 and MT7988 come with in-SoC SRAM dedicated for Ethernet
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DMA rings. Support using the SRAM without breaking existing device tree
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bindings, ie. only new SoC starting from MT7988 will have the SRAM
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declared as additional resource in device tree. For MT7981 and MT7986
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an offset on top of the main I/O base is used.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Link: https://lore.kernel.org/r/e45e0f230c63ad58869e8fe35b95a2fb8925b625.1692721443.git.daniel@makrotopia.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 88 ++++++++++++++++-----
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
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2 files changed, 78 insertions(+), 22 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1117,10 +1117,13 @@ static int mtk_init_fq_dma(struct mtk_et
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dma_addr_t dma_addr;
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int i;
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- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
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- cnt * soc->txrx.txd_size,
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- ð->phy_scratch_ring,
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- GFP_KERNEL);
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
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+ eth->scratch_ring = eth->sram_base;
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+ else
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+ eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
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+ cnt * soc->txrx.txd_size,
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+ ð->phy_scratch_ring,
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+ GFP_KERNEL);
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if (unlikely(!eth->scratch_ring))
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return -ENOMEM;
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@@ -2428,8 +2431,14 @@ static int mtk_tx_alloc(struct mtk_eth *
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if (!ring->buf)
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goto no_tx_mem;
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- ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
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- &ring->phys, GFP_KERNEL);
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+ if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
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+ ring->dma = eth->sram_base + ring_size * sz;
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+ ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz;
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+ } else {
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+ ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
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+ &ring->phys, GFP_KERNEL);
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+ }
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+
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if (!ring->dma)
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goto no_tx_mem;
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@@ -2528,8 +2537,7 @@ static void mtk_tx_clean(struct mtk_eth
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kfree(ring->buf);
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ring->buf = NULL;
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}
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-
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- if (ring->dma) {
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+ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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ring->dma_size * soc->txrx.txd_size,
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ring->dma, ring->phys);
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@@ -2548,9 +2556,14 @@ static int mtk_rx_alloc(struct mtk_eth *
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{
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const struct mtk_reg_map *reg_map = eth->soc->reg_map;
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struct mtk_rx_ring *ring;
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- int rx_data_len, rx_dma_size;
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+ int rx_data_len, rx_dma_size, tx_ring_size;
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int i;
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
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+ tx_ring_size = MTK_QDMA_RING_SIZE;
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+ else
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+ tx_ring_size = MTK_DMA_SIZE;
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+
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if (rx_flag == MTK_RX_FLAGS_QDMA) {
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if (ring_no)
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return -EINVAL;
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@@ -2585,9 +2598,20 @@ static int mtk_rx_alloc(struct mtk_eth *
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ring->page_pool = pp;
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}
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- ring->dma = dma_alloc_coherent(eth->dma_dev,
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- rx_dma_size * eth->soc->txrx.rxd_size,
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- &ring->phys, GFP_KERNEL);
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+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
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+ rx_flag != MTK_RX_FLAGS_NORMAL) {
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+ ring->dma = dma_alloc_coherent(eth->dma_dev,
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+ rx_dma_size * eth->soc->txrx.rxd_size,
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+ &ring->phys, GFP_KERNEL);
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+ } else {
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+ struct mtk_tx_ring *tx_ring = ð->tx_ring;
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+
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+ ring->dma = tx_ring->dma + tx_ring_size *
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+ eth->soc->txrx.txd_size * (ring_no + 1);
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+ ring->phys = tx_ring->phys + tx_ring_size *
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+ eth->soc->txrx.txd_size * (ring_no + 1);
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+ }
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+
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if (!ring->dma)
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return -ENOMEM;
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@@ -2672,7 +2696,7 @@ static int mtk_rx_alloc(struct mtk_eth *
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return 0;
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}
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-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
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+static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
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{
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int i;
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@@ -2695,7 +2719,7 @@ static void mtk_rx_clean(struct mtk_eth
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ring->data = NULL;
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}
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- if (ring->dma) {
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+ if (!in_sram && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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ring->dma_size * eth->soc->txrx.rxd_size,
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ring->dma, ring->phys);
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@@ -3058,7 +3082,7 @@ static void mtk_dma_free(struct mtk_eth
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for (i = 0; i < MTK_MAX_DEVS; i++)
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if (eth->netdev[i])
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netdev_reset_queue(eth->netdev[i]);
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- if (eth->scratch_ring) {
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+ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
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dma_free_coherent(eth->dma_dev,
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MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
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eth->scratch_ring, eth->phy_scratch_ring);
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@@ -3066,13 +3090,13 @@ static void mtk_dma_free(struct mtk_eth
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eth->phy_scratch_ring = 0;
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}
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mtk_tx_clean(eth);
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- mtk_rx_clean(eth, ð->rx_ring[0]);
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- mtk_rx_clean(eth, ð->rx_ring_qdma);
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+ mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
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+ mtk_rx_clean(eth, ð->rx_ring_qdma, false);
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if (eth->hwlro) {
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mtk_hwlro_rx_uninit(eth);
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for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
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- mtk_rx_clean(eth, ð->rx_ring[i]);
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+ mtk_rx_clean(eth, ð->rx_ring[i], false);
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}
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kfree(eth->scratch_head);
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@@ -4640,7 +4664,7 @@ static int mtk_sgmii_init(struct mtk_eth
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static int mtk_probe(struct platform_device *pdev)
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{
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- struct resource *res = NULL;
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+ struct resource *res = NULL, *res_sram;
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struct device_node *mac_np;
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struct mtk_eth *eth;
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int err, i;
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@@ -4660,6 +4684,20 @@ static int mtk_probe(struct platform_dev
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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eth->ip_align = NET_IP_ALIGN;
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
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+ /* SRAM is actual memory and supports transparent access just like DRAM.
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+ * Hence we don't require __iomem being set and don't need to use accessor
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+ * functions to read from or write to SRAM.
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+ */
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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+ eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
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+ if (IS_ERR(eth->sram_base))
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+ return PTR_ERR(eth->sram_base);
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+ } else {
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+ eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
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+ }
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+ }
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+
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spin_lock_init(ð->page_lock);
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spin_lock_init(ð->tx_irq_lock);
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spin_lock_init(ð->rx_irq_lock);
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@@ -4723,6 +4761,18 @@ static int mtk_probe(struct platform_dev
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err = -EINVAL;
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goto err_destroy_sgmii;
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}
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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+ res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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+ if (!res_sram) {
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+ err = -EINVAL;
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+ goto err_destroy_sgmii;
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+ }
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+ eth->phy_scratch_ring = res_sram->start;
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+ } else {
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+ eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
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+ }
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+ }
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}
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if (eth->soc->offload_version) {
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -139,6 +139,9 @@
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#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
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0x54C : 0x50C + (_x * 0x1000); })
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+/* Internal SRAM offset */
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+#define MTK_ETH_SRAM_OFFSET 0x40000
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+
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/* FE global misc reg*/
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#define MTK_FE_GLO_MISC 0x124
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@@ -938,6 +941,7 @@ enum mkt_eth_capabilities {
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MTK_RSTCTRL_PPE1_BIT,
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MTK_RSTCTRL_PPE2_BIT,
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MTK_U3_COPHY_V2_BIT,
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+ MTK_SRAM_BIT,
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/* MUX BITS*/
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MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
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@@ -973,6 +977,7 @@ enum mkt_eth_capabilities {
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#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
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#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
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#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
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+#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
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#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
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BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
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@@ -1048,14 +1053,14 @@ enum mkt_eth_capabilities {
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#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
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- MTK_RSTCTRL_PPE1)
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+ MTK_RSTCTRL_PPE1 | MTK_SRAM)
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#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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- MTK_RSTCTRL_PPE1)
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+ MTK_RSTCTRL_PPE1 | MTK_SRAM)
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#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
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- MTK_RSTCTRL_PPE2)
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+ MTK_RSTCTRL_PPE2 | MTK_SRAM)
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struct mtk_tx_dma_desc_info {
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dma_addr_t addr;
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@@ -1215,6 +1220,7 @@ struct mtk_eth {
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struct device *dev;
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struct device *dma_dev;
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void __iomem *base;
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+ void *sram_base;
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spinlock_t page_lock;
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spinlock_t tx_irq_lock;
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spinlock_t rx_irq_lock;
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