94 lines
3.4 KiB
Diff
94 lines
3.4 KiB
Diff
From 715878016984b2617f6c1f177c50039e12e7bd5b Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Thu, 30 Apr 2020 10:06:23 +0200
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Subject: [PATCH] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio
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function
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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We found out that we are unable to control the PERST# signal via the
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default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
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this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
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register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
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value of this register does not change the pin output when measuring
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with voltmeter.
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We do not know if this is a bug in the SOC, or if it works only when
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PCIe controller is in a certain state.
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Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready
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before training link") says that when this pin changes pinctrl mode
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from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
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moment.
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So currently the situation is that on A3700 boards the PERST# signal is
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asserted in U-Boot (because the code in U-Boot issues reset via this pin
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via GPIO mode), and then in Linux by the obscure and undocumented
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mechanism described by the above mentioned commit.
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We want to issue PERST# signal in a known way, therefore this patch
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changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
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reset-gpios property to the PCIe node in device tree files of
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EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
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has this property and uDPU does not have a PCIe port).
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Cc: Remi Pommarel <repk@triplefau.lt>
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Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/armada-3720-db.dts | 3 +++
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arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 +
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arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 4 ----
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arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +-
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4 files changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
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@@ -128,6 +128,9 @@
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/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
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&pcie0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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@@ -59,6 +59,7 @@
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phys = <&comphy1 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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};
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/* J6 */
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--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
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@@ -126,10 +126,6 @@
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};
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};
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-&pcie_reset_pins {
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- function = "gpio";
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-};
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-
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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@@ -318,7 +318,7 @@
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pcie_reset_pins: pcie-reset-pins {
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groups = "pcie1";
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- function = "pcie";
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+ function = "gpio";
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};
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pcie_clkreq_pins: pcie-clkreq-pins {
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