openwrt/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port...

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca956x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
label-mac-device = &eth0;
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&pcie {
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
read-only;
};
partition@20000 {
label = "partition-table";
reg = <0x020000 0x010000>;
read-only;
};
info: partition@30000 {
label = "info";
reg = <0x030000 0x010000>;
read-only;
};
partition@40000 {
compatible = "openwrt,elf";
label = "firmware";
reg = <0x040000 0xd80000>;
};
partition@dc0000 {
label = "config";
reg = <0xdc0000 0x030000>;
read-only;
};
/* df0000-f30000 undefined in vendor firmware */
partition@f30000 {
label = "log";
reg = <0xf30000 0x0c0000>;
read-only;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&pinmux {
mdio_pins: mdio_pins {
/* GPIO 10 as MDIO(0x20), GPIO 8 as MDC(0x21) */
pinctrl-single,bits = <0x8 0x00200021 0x00ff00ff>;
};
};
&mdio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy-mask = <0x10>;
phy4: ethernet-phy@4 {
reg = <4>;
reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy4>;
phy-mode = "sgmii";
pll-data = <0x03000000 0x00000101 0x00001313>;
nvmem-cells = <&macaddr_info_8>;
nvmem-cell-names = "mac-address";
qca956x-serdes-fixup;
gmac-config {
device = <&gmac>;
};
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
nvmem-cells = <&macaddr_info_8>;
nvmem-cell-names = "mac-address";
};
&info {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_info_8: macaddr@8 {
reg = <0x8 0x6>;
};
};