581 lines
11 KiB
Plaintext
581 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* Device tree for the CN9132-DB board.
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*/
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#include "cn9130.dtsi"
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#include "puzzle-thermal.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "iEi Puzzle-M902";
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compatible = "iei,puzzle-m902",
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"marvell,armada-ap807-quad", "marvell,armada-ap807";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp1_i2c0;
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i2c1 = &cp0_i2c0;
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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gpio3 = &cp1_gpio1;
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gpio4 = &cp1_gpio2;
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gpio5 = &cp2_gpio1;
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gpio6 = &cp2_gpio2;
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth1;
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ethernet2 = &cp0_eth2;
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ethernet3 = &cp1_eth0;
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ethernet4 = &cp1_eth1;
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ethernet5 = &cp1_eth2;
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ethernet6 = &cp2_eth0;
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ethernet7 = &cp2_eth1;
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ethernet8 = &cp2_eth2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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led-boot = &led_power;
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led-failsafe = &led_info;
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led-running = &led_power;
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led-upgrade = &led_info;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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gpio_keys {
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compatible = "gpio-keys";
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reset {
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label = "Reset";
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linux,code = <KEY_RESTART>;
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gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
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};
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};
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cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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cp2_usb3_0_phy0: cp2_usb3_phy0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp2_reg_usb3_vbus0>;
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};
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cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp2-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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cp2_usb3_0_phy1: cp2_usb3_phy1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp2_reg_usb3_vbus1>;
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};
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cp2_sfp_eth0: sfp-eth0 {
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compatible = "sff,sfp";
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i2c-bus = <&cp2_sfpp0_i2c>;
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los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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};
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&uart0 {
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status = "okay";
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};
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&cp0_uart0 {
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status = "okay";
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puzzle-mcu {
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compatible = "iei,wt61p803-puzzle";
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#address-cells = <1>;
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#size-cells = <1>;
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current-speed = <115200>;
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enable-beep;
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status = "okay";
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leds {
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compatible = "iei,wt61p803-puzzle-leds";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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led@0 {
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reg = <0>;
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label = "white:network";
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active-low;
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};
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led@1 {
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reg = <1>;
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label = "green:cloud";
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active-low;
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};
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led_info: led@2 {
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reg = <2>;
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label = "orange:info";
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active-low;
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};
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led_power: led@3 {
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reg = <3>;
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_YELLOW>;
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active-low;
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default-state = "on";
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};
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};
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hwmon {
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compatible = "iei,wt61p803-puzzle-hwmon";
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#address-cells = <1>;
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#size-cells = <0>;
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chassis_fan_group0: fan-group@0 {
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#cooling-cells = <2>;
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reg = <0x00>;
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cooling-levels = <0 159 195 211 223 241 255>;
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};
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};
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};
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};
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&ap_thermal_ic {
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PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
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};
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&cp0_thermal_ic {
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PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
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};
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/* on-board eMMC - U9 */
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&ap_sdhci0 {
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pinctrl-names = "default";
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bus-width = <8>;
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status = "okay";
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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};
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&cp0_crypto {
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status = "okay";
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};
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&cp0_xmdio {
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status = "okay";
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cp0_nbaset_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <2>;
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};
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cp0_nbaset_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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cp0_nbaset_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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/* SLM-1521-V2, CON9 */
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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phys = <&cp0_comphy2 0>;
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phy = <&cp0_nbaset_phy0>;
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};
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&cp0_eth1 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp0_comphy4 1>;
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phy = <&cp0_nbaset_phy1>;
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};
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&cp0_eth2 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp0_comphy1 2>;
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phy = <&cp0_nbaset_phy2>;
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};
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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rtc@32 {
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compatible = "epson,rx8130";
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reg = <0x32>;
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wakeup-source;
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};
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};
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&cp0_i2c1 {
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clock-frequency = <100000>;
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};
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/* SLM-1521-V2, CON6 */
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&cp0_sata0 {
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status = "okay";
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sata-port@1 {
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status = "okay";
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phys = <&cp0_comphy0 1>;
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};
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};
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&cp0_pcie2 {
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status = "okay";
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num-lanes = <1>;
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num-viewport = <8>;
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phys = <&cp0_comphy5 2>;
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};
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/* U55 */
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&cp0_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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reg = <0x700680 0x50>, /* control */
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<0x2000000 0x1000000>; /* CS0 */
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x1f0000>;
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};
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partition@1f0000 {
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label = "U-Boot ENV Factory";
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reg = <0x1f0000 0x10000>;
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};
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partition@200000 {
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label = "Reserved";
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reg = <0x200000 0x1f0000>;
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};
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partition@3f0000 {
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label = "U-Boot ENV";
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reg = <0x3f0000 0x10000>;
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};
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};
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};
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};
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&cp0_rtc {
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status = "disabled";
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
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marvell,pins = "mpp0", "mpp1", "mpp2",
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"mpp3", "mpp4", "mpp5",
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"mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11";
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marvell,function = "ge0";
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};
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cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
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marvell,pins = "mpp44", "mpp45", "mpp46",
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"mpp47", "mpp48", "mpp49",
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"mpp50", "mpp51", "mpp52",
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"mpp53", "mpp54", "mpp55";
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marvell,function = "ge1";
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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};
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};
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&cp0_usb3_1 {
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status = "okay";
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phys = <&cp0_comphy3 1>;
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phy-names = "usb";
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};
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/*
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* Instantiate the first connected CP115
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*/
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#define CP11X_NAME cp1
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#define CP11X_BASE f4000000
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#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f4600000
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#define CP11X_PCIE1_BASE f4620000
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#define CP11X_PCIE2_BASE f4640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp1_crypto {
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status = "okay";
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};
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&cp1_xmdio {
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status = "okay";
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cp1_nbaset_phy0: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <2>;
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};
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cp1_nbaset_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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cp1_nbaset_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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};
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};
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&cp1_ethernet {
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status = "okay";
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};
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/* CON50 */
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&cp1_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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phys = <&cp1_comphy2 0>;
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phy = <&cp1_nbaset_phy0>;
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};
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&cp1_eth1 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp1_comphy4 1>;
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phy = <&cp1_nbaset_phy1>;
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};
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&cp1_eth2 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp1_comphy1 2>;
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phy = <&cp1_nbaset_phy2>;
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};
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&cp1_gpio1 {
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status = "okay";
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};
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&cp1_gpio2 {
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status = "okay";
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};
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&cp1_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_i2c0_pins>;
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clock-frequency = <100000>;
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};
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&cp1_rtc {
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status = "disabled";
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};
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&cp1_syscon0 {
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cp1_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp1_i2c0_pins: cp1-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp1_spi0_pins: cp1-spi-pins-0 {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
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marvell,pins = "mpp3";
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marvell,function = "gpio";
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};
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};
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};
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&cp1_thermal_ic {
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PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
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};
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/*
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* Instantiate the second connected CP115
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*/
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#define CP11X_NAME cp2
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#define CP11X_BASE f6000000
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#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f6600000
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#define CP11X_PCIE1_BASE f6620000
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#define CP11X_PCIE2_BASE f6640000
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#include "armada-cp115.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp2_crypto {
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status = "okay";
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};
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&cp2_ethernet {
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status = "okay";
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};
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&cp2_xmdio {
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status = "okay";
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cp2_nbaset_phy0: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <2>;
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};
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cp2_nbaset_phy1: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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cp2_nbaset_phy2: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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};
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};
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/* SLM-1521-V2, CON9 */
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&cp2_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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phys = <&cp2_comphy2 0>;
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phy = <&cp2_nbaset_phy0>;
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};
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&cp2_eth1 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp2_comphy4 1>;
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phy = <&cp2_nbaset_phy1>;
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};
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&cp2_eth2 {
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status = "okay";
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phy-mode = "2500base-x";
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phys = <&cp2_comphy1 2>;
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phy = <&cp2_nbaset_phy2>;
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};
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&cp2_gpio1 {
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status = "okay";
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};
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&cp2_gpio2 {
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status = "okay";
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};
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&cp2_i2c0 {
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clock-frequency = <100000>;
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/* SLM-1521-V2 - U3 */
|
|
i2c-mux@72 {
|
|
compatible = "nxp,pca9544";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x72>;
|
|
cp2_sfpp0_i2c: i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
|
|
i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
/* U12 */
|
|
cp2_module_expander1: pca9555@21 {
|
|
compatible = "nxp,pca9555";
|
|
pinctrl-names = "default";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x21>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&cp2_rtc {
|
|
status = "disabled";
|
|
};
|
|
|
|
&cp2_syscon0 {
|
|
cp2_pinctrl: pinctrl {
|
|
compatible = "marvell,cp115-standalone-pinctrl";
|
|
cp2_i2c0_pins: cp2-i2c-pins-0 {
|
|
marvell,pins = "mpp37", "mpp38";
|
|
marvell,function = "i2c0";
|
|
};
|
|
};
|
|
};
|
|
|
|
&cp2_thermal_ic {
|
|
PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
|
|
};
|