508 lines
12 KiB
Plaintext
508 lines
12 KiB
Plaintext
#include <dt-bindings/net/qcom-ipq-ess.h>
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&soc {
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bias_pll_cc_clk: bias-pll-cc-clk {
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compatible = "fixed-clock";
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clock-frequency = <300000000>;
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clock-output-names = "bias_pll_cc_clk";
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#clock-cells = <0>;
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};
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bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
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compatible = "fixed-clock";
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clock-frequency = <416500000>;
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clock-output-names = "bias_pll_nss_noc_clk";
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#clock-cells = <0>;
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};
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edma: edma@3ab00000 {
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compatible = "qcom,edma";
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reg = <0x0 0x3ab00000 0x0 0xabe00>;
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reg-names = "edma-reg-base";
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qcom,txdesc-ring-start = <23>;
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qcom,txdesc-rings = <1>;
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qcom,txcmpl-ring-start = <23>;
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qcom,txcmpl-rings = <1>;
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qcom,rxfill-ring-start = <7>;
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qcom,rxfill-rings = <1>;
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qcom,rxdesc-ring-start = <15>;
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qcom,rxdesc-rings = <1>;
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interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&gcc GCC_EDMA_HW_RESET>;
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reset-names = "edma_rst";
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status = "disabled";
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};
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ess_instance: ess-instance {
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#address-cells = <1>;
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#size-cells = <1>;
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num_devices = <1>;
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switch: ess-switch@3a000000 {
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compatible = "qcom,ess-switch-ipq60xx";
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reg = <0x3a000000 0x1000000>;
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switch_access_mode = "local bus";
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clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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<&gcc GCC_CMN_12GPLL_SYS_CLK>,
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<&gcc GCC_UNIPHY0_AHB_CLK>,
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<&gcc GCC_UNIPHY0_SYS_CLK>,
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<&gcc GCC_UNIPHY1_AHB_CLK>,
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<&gcc GCC_UNIPHY1_SYS_CLK>,
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<&gcc GCC_PORT1_MAC_CLK>,
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<&gcc GCC_PORT2_MAC_CLK>,
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<&gcc GCC_PORT3_MAC_CLK>,
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<&gcc GCC_PORT4_MAC_CLK>,
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<&gcc GCC_PORT5_MAC_CLK>,
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<&gcc GCC_NSS_PPE_CLK>,
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<&gcc GCC_NSS_PPE_CFG_CLK>,
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<&gcc GCC_NSSNOC_PPE_CLK>,
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<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
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<&gcc GCC_NSS_EDMA_CLK>,
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<&gcc GCC_NSS_EDMA_CFG_CLK>,
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<&gcc GCC_NSS_PPE_IPE_CLK>,
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<&gcc GCC_MDIO_AHB_CLK>,
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<&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_NSS_CRYPTO_CLK>,
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<&gcc GCC_NSS_PTP_REF_CLK>,
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<&gcc GCC_NSS_PORT1_RX_CLK>,
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<&gcc GCC_NSS_PORT1_TX_CLK>,
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<&gcc GCC_NSS_PORT2_RX_CLK>,
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<&gcc GCC_NSS_PORT2_TX_CLK>,
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<&gcc GCC_NSS_PORT3_RX_CLK>,
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<&gcc GCC_NSS_PORT3_TX_CLK>,
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<&gcc GCC_NSS_PORT4_RX_CLK>,
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<&gcc GCC_NSS_PORT4_TX_CLK>,
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<&gcc GCC_NSS_PORT5_RX_CLK>,
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<&gcc GCC_NSS_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
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<&gcc NSS_PORT5_RX_CLK_SRC>,
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<&gcc NSS_PORT5_TX_CLK_SRC>,
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<&gcc GCC_SNOC_NSSNOC_CLK>;
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clock-names = "cmn_ahb_clk", "cmn_sys_clk",
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"uniphy0_ahb_clk", "uniphy0_sys_clk",
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"uniphy1_ahb_clk", "uniphy1_sys_clk",
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"port1_mac_clk", "port2_mac_clk",
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"port3_mac_clk", "port4_mac_clk",
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"port5_mac_clk",
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"nss_ppe_clk", "nss_ppe_cfg_clk",
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"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
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"nss_edma_clk", "nss_edma_cfg_clk",
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"nss_ppe_ipe_clk",
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"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
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"gcc_nssnoc_snoc_clk",
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"gcc_nss_crypto_clk",
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"gcc_nss_ptp_ref_clk",
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"nss_port1_rx_clk", "nss_port1_tx_clk",
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"nss_port2_rx_clk", "nss_port2_tx_clk",
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"nss_port3_rx_clk", "nss_port3_tx_clk",
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"nss_port4_rx_clk", "nss_port4_tx_clk",
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"nss_port5_rx_clk", "nss_port5_tx_clk",
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"uniphy0_port1_rx_clk",
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"uniphy0_port1_tx_clk",
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"uniphy0_port2_rx_clk",
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"uniphy0_port2_tx_clk",
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"uniphy0_port3_rx_clk",
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"uniphy0_port3_tx_clk",
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"uniphy0_port4_rx_clk",
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"uniphy0_port4_tx_clk",
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"uniphy0_port5_rx_clk",
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"uniphy0_port5_tx_clk",
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"uniphy1_port5_rx_clk",
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"uniphy1_port5_tx_clk",
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"nss_port5_rx_clk_src",
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"nss_port5_tx_clk_src",
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"gcc_snoc_nssnoc_clk";
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resets = <&gcc GCC_PPE_FULL_RESET>,
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<&gcc GCC_UNIPHY0_SOFT_RESET>,
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<&gcc GCC_UNIPHY0_XPCS_RESET>,
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<&gcc GCC_UNIPHY1_SOFT_RESET>,
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<&gcc GCC_UNIPHY1_XPCS_RESET>,
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<&gcc GCC_NSSPORT1_RESET>,
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<&gcc GCC_NSSPORT2_RESET>,
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<&gcc GCC_NSSPORT3_RESET>,
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<&gcc GCC_NSSPORT4_RESET>,
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<&gcc GCC_NSSPORT5_RESET>,
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<&gcc GCC_UNIPHY0_PORT1_ARES>,
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<&gcc GCC_UNIPHY0_PORT2_ARES>,
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<&gcc GCC_UNIPHY0_PORT3_ARES>,
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<&gcc GCC_UNIPHY0_PORT4_ARES>,
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<&gcc GCC_UNIPHY0_PORT5_ARES>,
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<&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
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<&gcc GCC_UNIPHY0_PORT_4_RESET>;
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reset-names = "ppe_rst", "uniphy0_soft_rst",
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"uniphy0_xpcs_rst", "uniphy1_soft_rst",
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"uniphy1_xpcs_rst", "nss_port1_rst",
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"nss_port2_rst", "nss_port3_rst",
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"nss_port4_rst", "nss_port5_rst",
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"uniphy0_port1_dis",
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"uniphy0_port2_dis",
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"uniphy0_port3_dis",
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"uniphy0_port4_dis",
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"uniphy0_port5_dis",
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"uniphy0_port_4_5_rst",
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"uniphy0_port_4_rst";
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mdio-bus = <&mdio>;
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switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
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switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/
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switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
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switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
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switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
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status = "disabled";
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bm_tick_mode = <0>; /* bm tick mode */
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tm_tick_mode = <0>; /* tm tick mode */
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port_scheduler_resource {
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port@0 {
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port_id = <0>;
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ucast_queue = <0 143>;
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mcast_queue = <256 271>;
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l0sp = <0 35>;
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l0cdrr = <0 47>;
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l0edrr = <0 47>;
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l1cdrr = <0 7>;
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l1edrr = <0 7>;
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};
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port@1 {
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port_id = <1>;
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ucast_queue = <144 159>;
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mcast_queue = <272 275>;
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l0sp = <36 39>;
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l0cdrr = <48 63>;
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l0edrr = <48 63>;
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l1cdrr = <8 11>;
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l1edrr = <8 11>;
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};
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port@2 {
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port_id = <2>;
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ucast_queue = <160 175>;
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mcast_queue = <276 279>;
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l0sp = <40 43>;
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l0cdrr = <64 79>;
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l0edrr = <64 79>;
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l1cdrr = <12 15>;
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l1edrr = <12 15>;
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};
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port@3 {
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port_id = <3>;
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ucast_queue = <176 191>;
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mcast_queue = <280 283>;
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l0sp = <44 47>;
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l0cdrr = <80 95>;
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l0edrr = <80 95>;
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l1cdrr = <16 19>;
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l1edrr = <16 19>;
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};
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port@4 {
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port_id = <4>;
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ucast_queue = <192 207>;
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mcast_queue = <284 287>;
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l0sp = <48 51>;
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l0cdrr = <96 111>;
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l0edrr = <96 111>;
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l1cdrr = <20 23>;
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l1edrr = <20 23>;
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};
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port@5 {
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port_id = <5>;
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ucast_queue = <208 223>;
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mcast_queue = <288 291>;
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l0sp = <52 55>;
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l0cdrr = <112 127>;
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l0edrr = <112 127>;
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l1cdrr = <24 27>;
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l1edrr = <24 27>;
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};
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port@6 {
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port_id = <6>;
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ucast_queue = <224 239>;
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mcast_queue = <292 295>;
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l0sp = <56 59>;
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l0cdrr = <128 143>;
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l0edrr = <128 143>;
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l1cdrr = <28 31>;
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l1edrr = <28 31>;
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};
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port@7 {
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port_id = <7>;
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ucast_queue = <240 255>;
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mcast_queue = <296 299>;
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l0sp = <60 63>;
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l0cdrr = <144 159>;
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l0edrr = <144 159>;
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l1cdrr = <32 35>;
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l1edrr = <32 35>;
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};
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};
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port_scheduler_config {
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port@0 {
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port_id = <0>;
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l1scheduler {
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group@0 {
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sp = <0 1>; /*L0 SPs*/
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/*cpri cdrr epri edrr*/
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cfg = <0 0 0 0>;
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};
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};
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l0scheduler {
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group@0 {
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/*unicast queues*/
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ucast_queue = <0 4 8>;
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/*multicast queues*/
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mcast_queue = <256 260>;
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/*sp cpricdrrepriedrr*/
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cfg = <0 0 0 0 0>;
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};
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group@1 {
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ucast_queue = <1 5 9>;
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mcast_queue = <257 261>;
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cfg = <0 1 1 1 1>;
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};
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group@2 {
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ucast_queue = <2 6 10>;
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mcast_queue = <258 262>;
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cfg = <0 2 2 2 2>;
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};
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group@3 {
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ucast_queue = <3 7 11>;
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mcast_queue = <259 263>;
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cfg = <0 3 3 3 3>;
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};
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};
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};
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port@1 {
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port_id = <1>;
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l1scheduler {
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group@0 {
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sp = <36>;
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cfg = <0 8 0 8>;
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};
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group@1 {
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sp = <37>;
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cfg = <1 9 1 9>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <144>;
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ucast_loop_pri = <16>;
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mcast_queue = <272>;
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mcast_loop_pri = <4>;
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cfg = <36 0 48 0 48>;
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};
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};
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};
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port@2 {
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port_id = <2>;
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l1scheduler {
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group@0 {
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sp = <40>;
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cfg = <0 12 0 12>;
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};
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group@1 {
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sp = <41>;
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cfg = <1 13 1 13>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <160>;
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ucast_loop_pri = <16>;
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mcast_queue = <276>;
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mcast_loop_pri = <4>;
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cfg = <40 0 64 0 64>;
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};
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};
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};
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port@3 {
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port_id = <3>;
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l1scheduler {
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group@0 {
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sp = <44>;
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cfg = <0 16 0 16>;
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};
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group@1 {
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sp = <45>;
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cfg = <1 17 1 17>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <176>;
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ucast_loop_pri = <16>;
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mcast_queue = <280>;
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mcast_loop_pri = <4>;
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cfg = <44 0 80 0 80>;
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};
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};
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};
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port@4 {
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port_id = <4>;
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l1scheduler {
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group@0 {
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sp = <48>;
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cfg = <0 20 0 20>;
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};
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group@1 {
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sp = <49>;
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cfg = <1 21 1 21>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <192>;
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ucast_loop_pri = <16>;
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mcast_queue = <284>;
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mcast_loop_pri = <4>;
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cfg = <48 0 96 0 96>;
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};
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};
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};
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port@5 {
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port_id = <5>;
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l1scheduler {
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group@0 {
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sp = <52>;
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cfg = <0 24 0 24>;
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};
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group@1 {
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sp = <53>;
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cfg = <1 25 1 25>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <208>;
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ucast_loop_pri = <16>;
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mcast_queue = <288>;
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mcast_loop_pri = <4>;
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cfg = <52 0 112 0 112>;
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};
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};
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};
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port@6 {
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port_id = <6>;
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l1scheduler {
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group@0 {
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sp = <56>;
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cfg = <0 28 0 28>;
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};
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group@1 {
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sp = <57>;
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cfg = <1 29 1 29>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <224>;
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ucast_loop_pri = <16>;
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mcast_queue = <292>;
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mcast_loop_pri = <4>;
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cfg = <56 0 128 0 128>;
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};
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};
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};
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port@7 {
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port_id = <7>;
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l1scheduler {
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group@0 {
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sp = <60>;
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cfg = <0 32 0 32>;
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};
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group@1 {
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sp = <61>;
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cfg = <1 33 1 33>;
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};
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};
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l0scheduler {
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group@0 {
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ucast_queue = <240>;
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ucast_loop_pri = <16>;
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mcast_queue = <296>;
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cfg = <60 0 144 0 144>;
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};
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};
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};
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};
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};
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ess-uniphy@7a00000 {
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compatible = "qcom,ess-uniphy";
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reg = <0x7a00000 0x30000>;
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uniphy_access_mode = "local bus";
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};
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};
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dp1: dp1 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <1>;
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reg = <0x0 0x3a001000 0x0 0x200>;
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qcom,mactype = <0>;
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local-mac-address = [000000000000];
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phy-mode = "psgmii";
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status = "disabled";
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};
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dp2: dp2 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <2>;
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reg = <0x0 0x3a001200 0x0 0x200>;
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qcom,mactype = <0>;
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local-mac-address = [000000000000];
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phy-mode = "psgmii";
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status = "disabled";
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};
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dp3: dp3 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <3>;
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reg = <0x0 0x3a001400 0x0 0x200>;
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qcom,mactype = <0>;
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local-mac-address = [000000000000];
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phy-mode = "psgmii";
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status = "disabled";
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};
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dp4: dp4 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <4>;
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reg = <0x0 0x3a001600 0x0 0x200>;
|
|
qcom,mactype = <0>;
|
|
local-mac-address = [000000000000];
|
|
phy-mode = "psgmii";
|
|
status = "disabled";
|
|
};
|
|
|
|
dp5: dp5 {
|
|
device_type = "network";
|
|
compatible = "qcom,nss-dp";
|
|
qcom,id = <5>;
|
|
reg = <0x0 0x3a001800 0x0 0x200>;
|
|
qcom,mactype = <0>;
|
|
local-mac-address = [000000000000];
|
|
phy-mode = "psgmii";
|
|
status = "disabled";
|
|
};
|
|
};
|