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0976b6c426
Set the PHY base address to 12 for mt7530 and 8 for others, which is based on the default setting for some devices from printing the register with the following command after it is written to by uboot during the boot cycle. `md 0x10117014 1` PHY_BASE option only uses 5 bits of the register, bits 16 to 20, so use 8-bit integer type. Set the option using the DTS property mediatek,ephy-base and create the gsw node if missing. Also, added a kernel message to display the EPHY base address. Note: If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf) then there is adverse effects with Atheros switches. Signed-off-by: Michael Pratt <mcpratt@pm.me>
168 lines
2.5 KiB
Plaintext
168 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "fon,fon2601", "ralink,mt7620a-soc";
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model = "Fon FON2601";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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leds {
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compatible = "gpio-leds";
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led_power: power_r {
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label = "red:power";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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};
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internet_g {
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label = "green:internet";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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net_g {
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label = "green:net";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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wifi_g {
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label = "green:wifi";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,padding = <32>;
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label = "firmware";
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reg = <0x50000 0xf90000>;
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};
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partition@fe0000 {
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label = "board_data";
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reg = <0xfe0000 0x20000>;
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read-only;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "uartf";
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function = "gpio";
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};
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nd_sd {
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groups = "nd_sd";
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function = "sd";
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};
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spi_cs {
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groups = "spi refclk";
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function = "spi refclk";
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii2_pins &mdio_pins>;
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mtd-mac-address = <&factory 0x4>;
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port@4 {
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status = "okay";
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phy-handle = <&phy4>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4-gmac;
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pa_pins>, <&wled_pins>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "pci14c3,7662";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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