31 lines
1.4 KiB
Diff
31 lines
1.4 KiB
Diff
From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 18 Feb 2024 01:59:59 +0000
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Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
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Without the SGM_REG_SEL clock enabled the system freezes if trying to
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access registers used by MT7981 clock drivers itself.
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Mark SGM_REG_SEL as critical to make sure it is always enabled to
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prevent freezes on boot depending on probe order.
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Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
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+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
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@@ -357,8 +357,9 @@ static const struct mtk_mux top_muxes[]
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
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sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
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0x1C0, 21),
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
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- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
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+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
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0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
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/* CLK_CFG_6 */
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