409 lines
16 KiB
Diff
409 lines
16 KiB
Diff
--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
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@@ -1042,6 +1042,11 @@
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#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
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#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
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+#define BB_PA_MODE_CFG0 0x1214
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+#define BB_PA_MODE_CFG1 0x1218
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+#define RF_PA_MODE_CFG0 0x121C
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+#define RF_PA_MODE_CFG1 0x1220
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+
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/*
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* EDCA_AC0_CFG:
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*/
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--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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@@ -3685,14 +3685,16 @@ static void rt2800_config_channel_rf7620
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rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
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rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
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- /* Default: XO=20MHz , SDM mode */
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- rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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- rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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- rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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-
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- rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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- rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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- rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ /* Default: XO=20MHz , SDM mode */
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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+ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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+ rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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+
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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+ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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+ rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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+ }
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rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
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@@ -3726,18 +3728,23 @@ static void rt2800_config_channel_rf7620
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rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
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}
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- if (conf_is_ht40(conf)) {
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- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
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- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
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- } else {
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- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
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- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ if (conf_is_ht40(conf)) {
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+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
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+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
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+ } else {
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+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
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+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
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+ }
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}
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- rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
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- rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
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- conf_is_ht40(conf) && (rf->channel == 11));
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- rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ rt2800_hw_get_chipeco(rt2x00dev) == 2) {
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
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+ rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
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+ conf_is_ht40(conf) && (rf->channel == 11));
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+ rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
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+ }
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if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
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if (conf_is_ht40(conf)) {
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@@ -3837,25 +3844,29 @@ static void rt2800_config_alc(struct rt2
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if (i == 10000)
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rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
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- if (chan->center_freq > 2457) {
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- bbp = rt2800_bbp_read(rt2x00dev, 30);
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- bbp = 0x40;
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- rt2800_bbp_write(rt2x00dev, 30, bbp);
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- rt2800_rfcsr_write(rt2x00dev, 39, 0);
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- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
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- rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
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- else
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- rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
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- } else {
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- bbp = rt2800_bbp_read(rt2x00dev, 30);
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- bbp = 0x1f;
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- rt2800_bbp_write(rt2x00dev, 30, bbp);
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- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
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- rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
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- else
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- rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ if (chan->center_freq > 2457) {
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+ bbp = rt2800_bbp_read(rt2x00dev, 30);
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+ bbp = 0x40;
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+ rt2800_bbp_write(rt2x00dev, 30, bbp);
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+ rt2800_rfcsr_write(rt2x00dev, 39, 0);
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+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
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+ rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
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+ else
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+ rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
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+ } else {
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+ bbp = rt2800_bbp_read(rt2x00dev, 30);
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+ bbp = 0x1f;
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+ rt2800_bbp_write(rt2x00dev, 30, bbp);
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+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
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+ rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
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+ else
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+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
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+ }
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}
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+
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rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
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rt2800_vco_calibration(rt2x00dev);
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@@ -5892,18 +5903,33 @@ static int rt2800_init_registers(struct
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} else if (rt2x00_rt(rt2x00dev, RT5350)) {
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rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
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} else if (rt2x00_rt(rt2x00dev, RT6352)) {
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- rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
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- rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
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- rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
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- rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
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- rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
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- rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
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- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
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- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
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- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
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- 0x3630363A);
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- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
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- 0x3630363A);
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+ if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
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+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
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+ 0x00000000);
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+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
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+ 0x000055FF);
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+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
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+ 0x00550055);
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+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
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+ 0x000055FF);
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+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
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+ 0x00550055);
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+ } else {
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
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+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
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+ rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
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+ rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
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+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
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+ 0x6C6C666C);
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+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
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+ 0x6C6C666C);
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+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
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+ 0x3630363A);
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+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
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+ 0x3630363A);
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+ }
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reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
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rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
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rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
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@@ -7068,14 +7094,16 @@ static void rt2800_init_bbp_6352(struct
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rt2800_bbp_write(rt2x00dev, 188, 0x00);
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rt2800_bbp_write(rt2x00dev, 189, 0x00);
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- rt2800_bbp_write(rt2x00dev, 91, 0x06);
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- rt2800_bbp_write(rt2x00dev, 92, 0x04);
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- rt2800_bbp_write(rt2x00dev, 93, 0x54);
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- rt2800_bbp_write(rt2x00dev, 99, 0x50);
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- rt2800_bbp_write(rt2x00dev, 148, 0x84);
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- rt2800_bbp_write(rt2x00dev, 167, 0x80);
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- rt2800_bbp_write(rt2x00dev, 178, 0xFF);
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- rt2800_bbp_write(rt2x00dev, 106, 0x13);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ rt2800_bbp_write(rt2x00dev, 91, 0x06);
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+ rt2800_bbp_write(rt2x00dev, 92, 0x04);
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+ rt2800_bbp_write(rt2x00dev, 93, 0x54);
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+ rt2800_bbp_write(rt2x00dev, 99, 0x50);
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+ rt2800_bbp_write(rt2x00dev, 148, 0x84);
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+ rt2800_bbp_write(rt2x00dev, 167, 0x80);
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+ rt2800_bbp_write(rt2x00dev, 178, 0xFF);
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+ rt2800_bbp_write(rt2x00dev, 106, 0x13);
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+ }
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/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
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rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
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@@ -10414,31 +10442,36 @@ static void rt2800_init_rfcsr_6352(struc
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rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
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rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
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- if (rt2800_clk_is_20mhz(rt2x00dev))
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- rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
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- else
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- rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
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- rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
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- rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
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- rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
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- rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
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- rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
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- rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
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- rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
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- rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
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- rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
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- rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
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- rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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- rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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-
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- rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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- rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
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- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
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+ if (rt2800_clk_is_20mhz(rt2x00dev))
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+ rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
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+ else
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+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
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+ rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
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+ rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
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+ rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
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+ rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
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+ rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
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+ rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
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+ rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
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+ rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
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+ rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
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+ rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
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+ rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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+ rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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+ }
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+
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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+ rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
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+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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+ }
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/* Initialize RF channel register to default value */
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rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
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@@ -10504,63 +10537,71 @@ static void rt2800_init_rfcsr_6352(struc
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rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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- rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
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- rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
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- rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
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- rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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-
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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-
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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-
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- /* Initialize RF channel register for DRQFN */
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
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+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
|
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+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
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+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
|
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
|
|
+ }
|
|
+
|
|
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
|
|
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
|
|
+
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
|
|
+ }
|
|
+
|
|
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
|
|
+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
|
|
+ /* Initialize RF channel register for DRQFN */
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
|
|
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
|
|
+ }
|
|
|
|
/* Initialize RF DC calibration register to default value */
|
|
rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
|
|
@@ -10623,12 +10664,17 @@ static void rt2800_init_rfcsr_6352(struc
|
|
rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
|
|
rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
|
|
|
|
- rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
|
|
- rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
|
|
- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
|
|
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
|
|
+ }
|
|
|
|
- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
|
|
- rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
|
|
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
|
|
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
|
|
+ }
|
|
|
|
rt2800_r_calibration(rt2x00dev);
|
|
rt2800_rf_self_txdc_cal(rt2x00dev);
|