71 lines
2.8 KiB
Diff
71 lines
2.8 KiB
Diff
From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001
|
|
From: Eugen Hristev <eugen.hristev@microchip.com>
|
|
Date: Fri, 13 Nov 2020 15:24:29 +0200
|
|
Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on
|
|
last PIO bank
|
|
|
|
Some products, like sama7g5, do not have a full last bank of PIO lines.
|
|
In this case for example, sama7g5 only has 8 lines for the PE bank.
|
|
PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
|
|
To cope with this situation, added a data attribute that is product dependent,
|
|
to specify the number of lines of the last bank.
|
|
In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
|
|
adjust the total number of lines accordingly.
|
|
This will avoid advertising 160 lines instead of the actual 136, as this
|
|
product supports, and to avoid reading/writing to invalid register addresses.
|
|
|
|
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
|
|
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
|
|
Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com
|
|
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
---
|
|
drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++--
|
|
1 file changed, 16 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
|
|
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
|
|
@@ -71,8 +71,15 @@
|
|
/* Custom pinconf parameters */
|
|
#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
|
|
|
|
+/**
|
|
+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
|
|
+ * @nbanks: number of PIO banks
|
|
+ * @last_bank_count: number of lines in the last bank (can be less than
|
|
+ * the rest of the banks).
|
|
+ */
|
|
struct atmel_pioctrl_data {
|
|
unsigned nbanks;
|
|
+ unsigned last_bank_count;
|
|
};
|
|
|
|
struct atmel_group {
|
|
@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct
|
|
* We can have up to 16 banks.
|
|
*/
|
|
static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
|
|
- .nbanks = 4,
|
|
+ .nbanks = 4,
|
|
+ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
|
|
};
|
|
|
|
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
|
|
- .nbanks = 5,
|
|
+ .nbanks = 5,
|
|
+ .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
|
|
};
|
|
|
|
static const struct of_device_id atmel_pctrl_of_match[] = {
|
|
@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl
|
|
atmel_pioctrl_data = match->data;
|
|
atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
|
|
atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
|
|
+ /* if last bank has limited number of pins, adjust accordingly */
|
|
+ if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
|
|
+ atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
|
|
+ atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
|
|
+ }
|
|
|
|
atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(atmel_pioctrl->reg_base))
|