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37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Thu, 19 Nov 2020 17:43:11 +0200
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Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout
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and characteristics
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This SoC has the 5th divisor for the mck0 master clock.
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Adapt the characteristics accordingly.
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Reported-by: Mihai Sain <mihai.sain@microchip.com>
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -775,13 +775,13 @@ static const struct clk_pll_characterist
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/* MCK0 characteristics. */
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static const struct clk_master_characteristics mck0_characteristics = {
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.output = { .min = 140000000, .max = 200000000 },
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- .divisors = { 1, 2, 4, 3 },
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+ .divisors = { 1, 2, 4, 3, 5 },
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.have_div3_pres = 1,
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};
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/* MCK0 layout. */
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static const struct clk_master_layout mck0_layout = {
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- .mask = 0x373,
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+ .mask = 0x773,
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.pres_shift = 4,
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.offset = 0x28,
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};
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