135 lines
3.9 KiB
Diff
135 lines
3.9 KiB
Diff
From cd72d75cfb216a7ef15ec8649e57b03b4fc48b62 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 27 May 2020 11:13:52 +0200
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Subject: [PATCH] clk: bcm: rpi: Use CCF boundaries instead of
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rolling our own
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The raspberrypi firmware clock driver has a min_rate / max_rate clamping by
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storing the info it needs in a private structure.
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However, the CCF already provides such a facility, so we can switch to it
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to remove the boilerplate.
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Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/clk/bcm/clk-raspberrypi.c | 49 ++++++++++++++++++++-----------
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1 file changed, 32 insertions(+), 17 deletions(-)
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--- a/drivers/clk/bcm/clk-raspberrypi.c
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+++ b/drivers/clk/bcm/clk-raspberrypi.c
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@@ -57,9 +57,6 @@ struct raspberrypi_clk_data {
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struct clk_hw hw;
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unsigned id;
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- unsigned long min_rate;
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- unsigned long max_rate;
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-
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struct raspberrypi_clk *rpi;
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};
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@@ -177,13 +174,11 @@ static int raspberrypi_fw_pll_set_rate(s
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static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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- struct raspberrypi_clk_data *data =
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- container_of(hw, struct raspberrypi_clk_data, hw);
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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- final_rate = clamp(req->rate, data->min_rate, data->max_rate);
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+ final_rate = clamp(req->rate, req->min_rate, req->max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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@@ -254,16 +249,15 @@ static struct clk_hw *raspberrypi_regist
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dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
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min_rate, max_rate);
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- data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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- data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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-
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data->hw.init = &init;
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ret = devm_clk_hw_register(rpi->dev, &data->hw);
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- if (ret)
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- return ERR_PTR(ret);
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+ if (!ret)
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+ clk_hw_set_rate_range(&data->hw,
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+ min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
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+ max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
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- return &data->hw;
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+ return ret;
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}
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static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
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@@ -299,22 +293,22 @@ static struct clk_hw *raspberrypi_regist
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return &raspberrypi_clk_pllb_arm.hw;
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}
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-static long raspberrypi_fw_dumb_round_rate(struct clk_hw *hw,
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- unsigned long rate,
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- unsigned long *parent_rate)
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+static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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{
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/*
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* The firmware will do the rounding but that isn't part of
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* the interface with the firmware, so we just do our best
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* here.
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*/
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- return rate;
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+ req->rate = clamp(req->rate, req->min_rate, req->max_rate);
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+ return 0;
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}
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static const struct clk_ops raspberrypi_firmware_clk_ops = {
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.is_prepared = raspberrypi_fw_is_prepared,
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.recalc_rate = raspberrypi_fw_get_rate,
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- .round_rate = raspberrypi_fw_dumb_round_rate,
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+ .determine_rate = raspberrypi_fw_dumb_determine_rate,
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.set_rate = raspberrypi_fw_set_rate,
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};
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@@ -324,6 +318,7 @@ static struct clk_hw *raspberrypi_clk_re
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{
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struct raspberrypi_clk_data *data;
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struct clk_init_data init = {};
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+ u32 min_rate, max_rate;
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int ret;
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if (id == RPI_FIRMWARE_ARM_CLK_ID) {
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@@ -351,10 +346,30 @@ static struct clk_hw *raspberrypi_clk_re
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data->hw.init = &init;
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+ ret = raspberrypi_clock_property(rpi->firmware, data,
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+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
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+ &min_rate);
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+ if (ret) {
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+ dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
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+ init.name, ret);
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+ return ERR_PTR(ret);
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+ }
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+
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+ ret = raspberrypi_clock_property(rpi->firmware, data,
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+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
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+ &max_rate);
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+ if (ret) {
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+ dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
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+ init.name, ret);
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+ return ERR_PTR(ret);
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+ }
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+
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ret = devm_clk_hw_register(rpi->dev, &data->hw);
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if (ret)
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return ERR_PTR(ret);
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+ clk_hw_set_rate_range(&data->hw, min_rate, max_rate);
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+
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return &data->hw;
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}
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