// SPDX-License-Identifier: GPL-2.0-or-later OR MIT #include #include "mt7620a_tplink_archer.dtsi" / { compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc"; model = "TP-Link Archer C2 v1"; aliases { led-boot = &led_wps; led-failsafe = &led_wps; led-running = &led_wps; led-upgrade = &led_wps; }; leds { compatible = "gpio-leds"; lan { function = LED_FUNCTION_LAN; color = ; gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; }; usb { function = LED_FUNCTION_USB; color = ; gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>; linux,default-trigger = "usbport"; }; led_wps: wps { function = LED_FUNCTION_WPS; color = ; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wan { function = LED_FUNCTION_WAN; color = ; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; }; wlan { function = LED_FUNCTION_WLAN; color = ; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy1tpt"; }; }; rtl8367rb { compatible = "realtek,rtl8367b"; cpu_port = <6>; realtek,extif1 = <1 0 1 1 1 1 1 1 2>; mii-bus = <&mdio0>; }; }; &state_default { gpio { groups = "i2c", "uartf", "wled", "ephy", "spi refclk"; function = "gpio"; }; }; ðernet { pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; nvmem-cells = <&macaddr_rom_f100 0>; nvmem-cell-names = "mac-address"; port@5 { status = "okay"; mediatek,fixed-link = <1000 1 1 1>; phy-mode = "rgmii"; }; mdio0: mdio-bus { status = "okay"; }; }; &wmac { nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>; nvmem-cell-names = "eeprom", "mac-address"; }; &wifi { nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>; nvmem-cell-names = "eeprom", "mac-address"; };