// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* Copyright (c) 2022, Matthew Hagan */ /dts-v1/; #include "ipq8074.dtsi" #include "ipq8074-ac-cpu.dtsi" #include "ipq8074-ess.dtsi" #include #include #include / { model = "Edgecore EAP102"; compatible = "edgecore,eap102", "qcom,ipq8074"; aliases { serial0 = &blsp1_uart5; serial1 = &blsp1_uart3; led-boot = &led_system_green; led-failsafe = &led_system_green; led-running = &led_system_green; led-upgrade = &led_system_green; /* Aliases as required by u-boot to patch MAC addresses */ ethernet0 = &dp6; ethernet1 = &dp5; label-mac-device = &dp5; }; chosen { stdout-path = "serial0:115200n8"; bootargs-append = " root=/dev/ubiblock0_1"; }; keys { compatible = "gpio-keys"; pinctrl-0 = <&button_pins>; pinctrl-names = "default"; reset { label = "reset"; gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; linux,code = ; }; }; leds { compatible = "gpio-leds"; led_wanpoe { label = "green:wanpoe"; gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>; }; led_wlan2g { label = "green:wlan2g"; gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy1radio"; }; led_wlan5g { label = "green:wlan5g"; gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0radio"; }; led_system_green: led_system { function = LED_FUNCTION_POWER; color = ; gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; }; }; }; &tlmm { mdio_pins: mdio-pins { mdc { pins = "gpio68"; function = "mdc"; drive-strength = <8>; bias-pull-up; }; mdio { pins = "gpio69"; function = "mdio"; drive-strength = <8>; bias-pull-up; }; }; button_pins: button_pins { reset_button { pins = "gpio66"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; }; }; &blsp1_spi1 { status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "0:sbl1"; reg = <0x0 0x50000>; read-only; }; partition@50000 { label = "0:mibib"; reg = <0x50000 0x10000>; read-only; }; partition@60000 { label = "0:bootconfig"; reg = <0x60000 0x20000>; read-only; }; partition@80000 { label = "0:bootconfig1"; reg = <0x80000 0x20000>; read-only; }; partition@a0000 { label = "0:qsee"; reg = <0xa0000 0x180000>; read-only; }; partition@220000 { label = "0:qsee_1"; reg = <0x220000 0x180000>; read-only; }; partition@3a0000 { label = "0:devcfg"; reg = <0x3a0000 0x10000>; read-only; }; partition@3b0000 { label = "0:devcfg_1"; reg = <0x3b0000 0x10000>; read-only; }; partition@3c0000 { label = "0:apdp"; reg = <0x3c0000 0x10000>; read-only; }; partition@3d0000 { label = "0:apdp_1"; reg = <0x3d0000 0x10000>; read-only; }; partition@3e0000 { label = "0:rpm"; reg = <0x3e0000 0x40000>; read-only; }; partition@420000 { label = "0:rpm_1"; reg = <0x420000 0x40000>; read-only; }; partition@460000 { label = "0:cdt"; reg = <0x460000 0x10000>; read-only; }; partition@470000 { label = "0:cdt_1"; reg = <0x470000 0x10000>; read-only; }; partition@480000 { label = "0:appsblenv"; reg = <0x480000 0x10000>; }; partition@490000 { label = "0:appsbl"; reg = <0x490000 0xc0000>; read-only; }; partition@550000 { label = "0:appsbl_1"; reg = <0x530000 0xc0000>; read-only; }; partition@610000 { label = "0:art"; reg = <0x610000 0x40000>; read-only; }; partition@650000 { label = "0:ethphyfw"; reg = <0x650000 0x80000>; read-only; }; partition@6d0000 { label = "0:product_info"; reg = <0x6d0000 0x80000>; read-only; }; partition@750000 { label = "priv_data1"; reg = <0x750000 0x10000>; read-only; }; partition@760000 { label = "priv_data2"; reg = <0x760000 0x10000>; read-only; }; }; }; }; &blsp1_uart3 { status = "okay"; }; &blsp1_uart5 { status = "okay"; }; &crypto { status = "okay"; }; &cryptobam { status = "okay"; }; &prng { status = "okay"; }; &qpic_bam { status = "okay"; }; &qusb_phy_0 { status = "okay"; }; &ssphy_0 { status = "okay"; }; &usb_0 { status = "okay"; }; &qpic_nand { status = "okay"; nand@0 { reg = <0>; nand-ecc-strength = <8>; nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "rootfs1"; reg = <0x0000000 0x3400000>; }; partition@3400000 { label = "0:wififw"; reg = <0x3400000 0x800000>; read-only; }; partition@3c00000 { label = "rootfs2"; reg = <0x3c00000 0x3400000>; }; partition@7000000 { label = "0:wififw_1"; reg = <0x7000000 0x800000>; read-only; }; }; }; }; &mdio { status = "okay"; pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; qca8081_24: ethernet-phy@24 { compatible = "ethernet-phy-id004d.d101"; reg = <24>; reset-deassert-us = <10000>; reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; }; qca8081_28: ethernet-phy@28 { compatible = "ethernet-phy-id004d.d101"; reg = <28>; reset-deassert-us = <10000>; reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; }; }; &switch { status = "okay"; switch_lan_bmp = ; /* lan port bitmap */ switch_wan_bmp = ; /* wan port bitmap */ switch_mac_mode1 = ; /* mac mode for uniphy instance1*/ switch_mac_mode2 = ; /* mac mode for uniphy instance2*/ qcom,port_phyinfo { port@5 { port_id = <5>; phy_address = <24>; port_mac_sel = "QGMAC_PORT"; }; port@6 { port_id = <6>; phy_address = <28>; port_mac_sel = "QGMAC_PORT"; }; }; }; &edma { status = "okay"; }; &dp5 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&qca8081_24>; label = "lan"; }; &dp6 { status = "okay"; phy-handle = <&qca8081_28>; label = "wan"; }; &wifi { status = "okay"; qcom,ath11k-calibration-variant = "Edgecore-EAP102"; };