airoha: remove 5.15 support
Now that 6.1 is default, remove 5.15 support. Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
parent
cbc2664d1d
commit
fd58b1a8bc
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@ -1,271 +0,0 @@
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_AIROHA=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_MULTI_V7=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARM=y
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_CPU_SUSPEND=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_HEAVY_MB=y
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# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
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CONFIG_ARM_L1_CACHE_SHIFT=6
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CONFIG_ARM_L1_CACHE_SHIFT_6=y
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CONFIG_ARM_PATCH_IDIV=y
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_PSCI=y
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_SMMU is not set
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CONFIG_ARM_THUMB=y
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CONFIG_ARM_UNWIND=y
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CONFIG_ARM_VIRT_EXT=y
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CONFIG_ATAGS=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_CACHE_L2X0=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_FROM_BOOTLOADER=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_EN7523=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_32v7=y
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CONFIG_CPU_ABRT_EV7=y
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CONFIG_CPU_CACHE_V7=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_HAS_ASID=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SPECTRE=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_HASH_INFO=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_ZSTD=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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CONFIG_DEBUG_MISC=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_REMAP=y
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CONFIG_DTC=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MIGRATION=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_PINCTRL_GROUPS=y
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CONFIG_GENERIC_PINMUX_FUNCTIONS=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GENERIC_VDSO_32=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_EN7523=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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# CONFIG_HARDEN_BRANCH_HISTORY is not set
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# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HAVE_SMP=y
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CONFIG_HOTPLUG_CPU=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ_FIXED=0
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_IOMMU_DEBUGFS is not set
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# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
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# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
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CONFIG_IOMMU_SUPPORT=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_TIME_ACCOUNTING=y
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CONFIG_IRQ_WORK=y
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# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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CONFIG_MIGRATION=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_NAND_CORE=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_ECC_SW_HAMMING=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_FIT_FW=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_BEB_LIMIT=20
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CONFIG_MTD_UBI_BLOCK=y
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NLS=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_NR_CPUS=2
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CONFIG_NVMEM=y
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CONFIG_NVMEM_SYSFS=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_OUTER_CACHE=y
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CONFIG_OUTER_CACHE_SYNC=y
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CONFIG_PADATA=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PARTITION_PERCPU=y
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_MEDIATEK=y
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CONFIG_PCIE_PME=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI_IRQ_DOMAIN=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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CONFIG_PINCTRL=y
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CONFIG_PM=y
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CONFIG_PM_CLK=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_PWM=y
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CONFIG_PWM_SYSFS=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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CONFIG_REGMAP=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RFS_ACCEL=y
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CONFIG_RPS=y
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CONFIG_RWSEM_SPIN_ON_OWNER=y
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CONFIG_SCSI=y
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CONFIG_SCSI_COMMON=y
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_FSL=y
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# CONFIG_SERIAL_8250_SHARE_IRQ is not set
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CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SGL_ALLOC=y
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CONFIG_SG_POOL=y
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CONFIG_SMP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_SOCK_RX_QUEUE_MAPPING=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPI=y
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CONFIG_SPI_AIROHA_EN7523=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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CONFIG_SRCU=y
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CONFIG_STACKTRACE=y
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# CONFIG_SWAP is not set
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CONFIG_SWPHY=y
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CONFIG_SWP_EMULATE=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TIMER_OF=y
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CONFIG_TIMER_PROBE=y
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CONFIG_TREE_RCU=y
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CONFIG_TREE_SRCU=y
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CONFIG_UBIFS_FS=y
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CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
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CONFIG_UNWINDER_ARM=y
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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CONFIG_USB_SUPPORT=y
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CONFIG_USB_XHCI_HCD=y
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# CONFIG_USB_XHCI_PLATFORM is not set
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CONFIG_USE_OF=y
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# CONFIG_VFP is not set
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CONFIG_WATCHDOG_CORE=y
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# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
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CONFIG_XPS=y
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CONFIG_XXHASH=y
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CONFIG_XZ_DEC_ARM=y
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_ZBOOT_ROM_BSS=0
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CONFIG_ZBOOT_ROM_TEXT=0
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CONFIG_ZLIB_DEFLATE=y
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CONFIG_ZLIB_INFLATE=y
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CONFIG_ZSTD_COMPRESS=y
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CONFIG_ZSTD_DECOMPRESS=y
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@ -1,2 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += airoha.o
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@ -1,16 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Device Tree support for Airoha SoCs
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*
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* Copyright (c) 2022 Felix Fietkau <nbd@nbd.name>
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*/
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#include <asm/mach/arch.h>
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static const char * const airoha_board_dt_compat[] = {
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"airoha,en7523",
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NULL,
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};
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DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)")
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.dt_compat = airoha_board_dt_compat,
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MACHINE_END
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@ -1,351 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#define REG_PCI_CONTROL 0x88
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#define REG_PCI_CONTROL_PERSTOUT BIT(29)
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#define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
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#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
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#define REG_GSW_CLK_DIV_SEL 0x1b4
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#define REG_EMI_CLK_DIV_SEL 0x1b8
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#define REG_BUS_CLK_DIV_SEL 0x1bc
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#define REG_SPI_CLK_DIV_SEL 0x1c4
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#define REG_SPI_CLK_FREQ_SEL 0x1c8
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#define REG_NPU_CLK_DIV_SEL 0x1fc
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#define REG_CRYPTO_CLKSRC 0x200
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#define REG_RESET_CONTROL 0x834
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#define REG_RESET_CONTROL_PCIEHB BIT(29)
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#define REG_RESET_CONTROL_PCIE1 BIT(27)
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#define REG_RESET_CONTROL_PCIE2 BIT(26)
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struct en_clk_desc {
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int id;
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const char *name;
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u32 base_reg;
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u8 base_bits;
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u8 base_shift;
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union {
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const unsigned int *base_values;
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unsigned int base_value;
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};
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size_t n_base_values;
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u16 div_reg;
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u8 div_bits;
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u8 div_shift;
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u16 div_val0;
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u8 div_step;
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};
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struct en_clk_gate {
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void __iomem *base;
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struct clk_hw hw;
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};
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static const u32 gsw_base[] = { 400000000, 500000000 };
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static const u32 emi_base[] = { 333000000, 400000000 };
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static const u32 bus_base[] = { 500000000, 540000000 };
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static const u32 slic_base[] = { 100000000, 3125000 };
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static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
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static const struct en_clk_desc en7523_base_clks[] = {
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{
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.id = EN7523_CLK_GSW,
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.name = "gsw",
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.base_reg = REG_GSW_CLK_DIV_SEL,
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.base_bits = 1,
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.base_shift = 8,
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.base_values = gsw_base,
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.n_base_values = ARRAY_SIZE(gsw_base),
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.div_bits = 3,
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.div_shift = 0,
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.div_step = 1,
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}, {
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.id = EN7523_CLK_EMI,
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.name = "emi",
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.base_reg = REG_EMI_CLK_DIV_SEL,
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.base_bits = 1,
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.base_shift = 8,
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.base_values = emi_base,
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.n_base_values = ARRAY_SIZE(emi_base),
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.div_bits = 3,
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.div_shift = 0,
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.div_step = 1,
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}, {
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.id = EN7523_CLK_BUS,
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.name = "bus",
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.base_reg = REG_BUS_CLK_DIV_SEL,
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.base_bits = 1,
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.base_shift = 8,
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.base_values = bus_base,
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.n_base_values = ARRAY_SIZE(bus_base),
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.div_bits = 3,
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.div_shift = 0,
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.div_step = 1,
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}, {
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.id = EN7523_CLK_SLIC,
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.name = "slic",
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.base_reg = REG_SPI_CLK_FREQ_SEL,
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.base_bits = 1,
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.base_shift = 0,
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.base_values = slic_base,
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.n_base_values = ARRAY_SIZE(slic_base),
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.div_reg = REG_SPI_CLK_DIV_SEL,
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.div_bits = 5,
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.div_shift = 24,
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.div_val0 = 20,
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.div_step = 2,
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}, {
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.id = EN7523_CLK_SPI,
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.name = "spi",
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.base_reg = REG_SPI_CLK_DIV_SEL,
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.base_value = 400000000,
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.div_bits = 5,
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.div_shift = 8,
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.div_val0 = 40,
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.div_step = 2,
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}, {
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.id = EN7523_CLK_NPU,
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.name = "npu",
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.base_reg = REG_NPU_CLK_DIV_SEL,
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.base_bits = 2,
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.base_shift = 8,
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.base_values = npu_base,
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.n_base_values = ARRAY_SIZE(npu_base),
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.div_bits = 3,
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.div_shift = 0,
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.div_step = 1,
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}, {
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.id = EN7523_CLK_CRYPTO,
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.name = "crypto",
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.base_reg = REG_CRYPTO_CLKSRC,
|
||||
.base_bits = 1,
|
||||
.base_shift = 8,
|
||||
.base_values = emi_base,
|
||||
.n_base_values = ARRAY_SIZE(emi_base),
|
||||
}
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_en7523[] = {
|
||||
{ .compatible = "airoha,en7523-scu", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
|
||||
{
|
||||
const struct en_clk_desc *desc = &en7523_base_clks[i];
|
||||
u32 val;
|
||||
|
||||
if (!desc->base_bits)
|
||||
return desc->base_value;
|
||||
|
||||
val = readl(base + desc->base_reg);
|
||||
val >>= desc->base_shift;
|
||||
val &= (1 << desc->base_bits) - 1;
|
||||
|
||||
if (val >= desc->n_base_values)
|
||||
return 0;
|
||||
|
||||
return desc->base_values[val];
|
||||
}
|
||||
|
||||
static u32 en7523_get_div(void __iomem *base, int i)
|
||||
{
|
||||
const struct en_clk_desc *desc = &en7523_base_clks[i];
|
||||
u32 reg, val;
|
||||
|
||||
if (!desc->div_bits)
|
||||
return 1;
|
||||
|
||||
reg = desc->div_reg ? desc->div_reg : desc->base_reg;
|
||||
val = readl(base + reg);
|
||||
val >>= desc->div_shift;
|
||||
val &= (1 << desc->div_bits) - 1;
|
||||
|
||||
if (!val && desc->div_val0)
|
||||
return desc->div_val0;
|
||||
|
||||
return (val + 1) * desc->div_step;
|
||||
}
|
||||
|
||||
static int en7523_pci_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
|
||||
|
||||
return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
|
||||
}
|
||||
|
||||
static int en7523_pci_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
|
||||
void __iomem *np_base = cg->base;
|
||||
u32 val, mask;
|
||||
|
||||
/* Need to pull device low before reset */
|
||||
val = readl(np_base + REG_PCI_CONTROL);
|
||||
val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
|
||||
writel(val, np_base + REG_PCI_CONTROL);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
/* Enable PCIe port 1 */
|
||||
val |= REG_PCI_CONTROL_REFCLK_EN1;
|
||||
writel(val, np_base + REG_PCI_CONTROL);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
/* Reset to default */
|
||||
val = readl(np_base + REG_RESET_CONTROL);
|
||||
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
|
||||
REG_RESET_CONTROL_PCIEHB;
|
||||
writel(val & ~mask, np_base + REG_RESET_CONTROL);
|
||||
usleep_range(1000, 2000);
|
||||
writel(val | mask, np_base + REG_RESET_CONTROL);
|
||||
msleep(100);
|
||||
writel(val & ~mask, np_base + REG_RESET_CONTROL);
|
||||
usleep_range(5000, 10000);
|
||||
|
||||
/* Release device */
|
||||
mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
|
||||
val = readl(np_base + REG_PCI_CONTROL);
|
||||
writel(val & ~mask, np_base + REG_PCI_CONTROL);
|
||||
usleep_range(1000, 2000);
|
||||
writel(val | mask, np_base + REG_PCI_CONTROL);
|
||||
msleep(250);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void en7523_pci_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
|
||||
void __iomem *np_base = cg->base;
|
||||
u32 val;
|
||||
|
||||
val = readl(np_base + REG_PCI_CONTROL);
|
||||
val &= ~REG_PCI_CONTROL_REFCLK_EN1;
|
||||
writel(val, np_base + REG_PCI_CONTROL);
|
||||
}
|
||||
|
||||
static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
|
||||
void __iomem *np_base)
|
||||
{
|
||||
static const struct clk_ops pcie_gate_ops = {
|
||||
.is_enabled = en7523_pci_is_enabled,
|
||||
.prepare = en7523_pci_prepare,
|
||||
.unprepare = en7523_pci_unprepare,
|
||||
};
|
||||
struct clk_init_data init = {
|
||||
.name = "pcie",
|
||||
.ops = &pcie_gate_ops,
|
||||
};
|
||||
struct en_clk_gate *cg;
|
||||
|
||||
cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL);
|
||||
if (!cg)
|
||||
return NULL;
|
||||
|
||||
cg->base = np_base;
|
||||
cg->hw.init = &init;
|
||||
en7523_pci_unprepare(&cg->hw);
|
||||
|
||||
if (clk_hw_register(dev, &cg->hw))
|
||||
return NULL;
|
||||
|
||||
return &cg->hw;
|
||||
}
|
||||
|
||||
static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
|
||||
void __iomem *base, void __iomem *np_base)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
u32 rate;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
|
||||
const struct en_clk_desc *desc = &en7523_base_clks[i];
|
||||
|
||||
rate = en7523_get_base_rate(base, i);
|
||||
rate /= en7523_get_div(base, i);
|
||||
|
||||
hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register clk %s: %ld\n",
|
||||
desc->name, PTR_ERR(hw));
|
||||
continue;
|
||||
}
|
||||
|
||||
clk_data->hws[desc->id] = hw;
|
||||
}
|
||||
|
||||
hw = en7523_register_pcie_clk(dev, np_base);
|
||||
clk_data->hws[EN7523_CLK_PCIE] = hw;
|
||||
|
||||
clk_data->num = EN7523_NUM_CLOCKS;
|
||||
}
|
||||
|
||||
static int en7523_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base, *np_base;
|
||||
int r;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
np_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(np_base))
|
||||
return PTR_ERR(np_base);
|
||||
|
||||
clk_data = devm_kzalloc(&pdev->dev,
|
||||
struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_en7523_drv = {
|
||||
.probe = en7523_clk_probe,
|
||||
.driver = {
|
||||
.name = "clk-en7523",
|
||||
.of_match_table = of_match_clk_en7523,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_en7523_init(void)
|
||||
{
|
||||
return platform_driver_register(&clk_en7523_drv);
|
||||
}
|
||||
|
||||
arch_initcall(clk_en7523_init);
|
||||
|
|
@ -1,137 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/property.h>
|
||||
|
||||
#define AIROHA_GPIO_MAX 32
|
||||
|
||||
/**
|
||||
* airoha_gpio_ctrl - Airoha GPIO driver data
|
||||
* @gc: Associated gpio_chip instance.
|
||||
* @data: The data register.
|
||||
* @dir0: The direction register for the lower 16 pins.
|
||||
* @dir1: The direction register for the higher 16 pins.
|
||||
* @output: The output enable register.
|
||||
*/
|
||||
struct airoha_gpio_ctrl {
|
||||
struct gpio_chip gc;
|
||||
void __iomem *data;
|
||||
void __iomem *dir[2];
|
||||
void __iomem *output;
|
||||
};
|
||||
|
||||
static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
|
||||
{
|
||||
return container_of(gc, struct airoha_gpio_ctrl, gc);
|
||||
}
|
||||
|
||||
static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
|
||||
int val, int out)
|
||||
{
|
||||
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
|
||||
u32 dir = ioread32(ctrl->dir[gpio / 16]);
|
||||
u32 output = ioread32(ctrl->output);
|
||||
u32 mask = BIT((gpio % 16) * 2);
|
||||
|
||||
if (out) {
|
||||
dir |= mask;
|
||||
output |= BIT(gpio);
|
||||
} else {
|
||||
dir &= ~mask;
|
||||
output &= ~BIT(gpio);
|
||||
}
|
||||
|
||||
iowrite32(dir, ctrl->dir[gpio / 16]);
|
||||
|
||||
if (out)
|
||||
gc->set(gc, gpio, val);
|
||||
|
||||
iowrite32(output, ctrl->output);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
|
||||
int val)
|
||||
{
|
||||
return airoha_dir_set(gc, gpio, val, 1);
|
||||
}
|
||||
|
||||
static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
return airoha_dir_set(gc, gpio, 0, 0);
|
||||
}
|
||||
|
||||
static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
|
||||
u32 dir = ioread32(ctrl->dir[gpio / 16]);
|
||||
u32 mask = BIT((gpio % 16) * 2);
|
||||
|
||||
return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static int airoha_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct airoha_gpio_ctrl *ctrl;
|
||||
int err;
|
||||
|
||||
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
ctrl->data = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(ctrl->data))
|
||||
return PTR_ERR(ctrl->data);
|
||||
|
||||
ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(ctrl->dir[0]))
|
||||
return PTR_ERR(ctrl->dir[0]);
|
||||
|
||||
ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
|
||||
if (IS_ERR(ctrl->dir[1]))
|
||||
return PTR_ERR(ctrl->dir[1]);
|
||||
|
||||
ctrl->output = devm_platform_ioremap_resource(pdev, 3);
|
||||
if (IS_ERR(ctrl->output))
|
||||
return PTR_ERR(ctrl->output);
|
||||
|
||||
err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
|
||||
NULL, NULL, NULL, 0);
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "unable to init generic GPIO");
|
||||
|
||||
ctrl->gc.ngpio = AIROHA_GPIO_MAX;
|
||||
ctrl->gc.owner = THIS_MODULE;
|
||||
ctrl->gc.direction_output = airoha_dir_out;
|
||||
ctrl->gc.direction_input = airoha_dir_in;
|
||||
ctrl->gc.get_direction = airoha_get_dir;
|
||||
|
||||
return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
|
||||
}
|
||||
|
||||
static const struct of_device_id airoha_gpio_of_match[] = {
|
||||
{ .compatible = "airoha,en7523-gpio" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
|
||||
|
||||
static struct platform_driver airoha_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "airoha-gpio",
|
||||
.of_match_table = airoha_gpio_of_match,
|
||||
},
|
||||
.probe = airoha_gpio_probe,
|
||||
};
|
||||
module_platform_driver(airoha_gpio_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Airoha GPIO support");
|
||||
MODULE_AUTHOR("John Crispin <john@phrozen.org>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
|
||||
#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
|
||||
|
||||
#define EN7523_CLK_GSW 0
|
||||
#define EN7523_CLK_EMI 1
|
||||
#define EN7523_CLK_BUS 2
|
||||
#define EN7523_CLK_SLIC 3
|
||||
#define EN7523_CLK_SPI 4
|
||||
#define EN7523_CLK_NPU 5
|
||||
#define EN7523_CLK_CRYPTO 6
|
||||
#define EN7523_CLK_PCIE 7
|
||||
|
||||
#define EN7523_NUM_CLOCKS 8
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -572,6 +572,18 @@ config ARCH_VIRT
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
|
||||
+config ARCH_AIROHA
|
||||
+ bool "Airoha SoC Support"
|
||||
+ depends on ARCH_MULTI_V7
|
||||
+ select ARM_AMBA
|
||||
+ select ARM_GIC
|
||||
+ select ARM_GIC_V3
|
||||
+ select ARM_PSCI
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
+ select COMMON_CLK
|
||||
+ help
|
||||
+ Support for Airoha EN7523 SoCs
|
||||
+
|
||||
#
|
||||
# This is sorted alphabetically by mach-* pathname. However, plat-*
|
||||
# Kconfigs may be included either alphabetically (according to the
|
||||
--- a/arch/arm/Makefile
|
||||
+++ b/arch/arm/Makefile
|
||||
@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
machine-$(CONFIG_ARCH_ACTIONS) += actions
|
||||
+machine-$(CONFIG_ARCH_AIROHA) += airoha
|
||||
machine-$(CONFIG_ARCH_ALPINE) += alpine
|
||||
machine-$(CONFIG_ARCH_ARTPEC) += artpec
|
||||
machine-$(CONFIG_ARCH_ASPEED) += aspeed
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
--- a/drivers/clk/Kconfig
|
||||
+++ b/drivers/clk/Kconfig
|
||||
@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP
|
||||
help
|
||||
If you say yes here you get support for the CS2000 clock multiplier.
|
||||
|
||||
+config COMMON_CLK_EN7523
|
||||
+ bool "Clock driver for Airoha EN7523 SoC system clocks"
|
||||
+ depends on OF
|
||||
+ depends on ARCH_AIROHA || COMPILE_TEST
|
||||
+ default ARCH_AIROHA
|
||||
+ help
|
||||
+ This driver provides the fixed clocks and gates present on Airoha
|
||||
+ ARM silicon.
|
||||
+
|
||||
config COMMON_CLK_FSL_FLEXSPI
|
||||
tristate "Clock driver for FlexSPI on Layerscape SoCs"
|
||||
depends on ARCH_LAYERSCAPE || COMPILE_TEST
|
||||
--- a/drivers/clk/Makefile
|
||||
+++ b/drivers/clk/Makefile
|
||||
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-
|
||||
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
|
||||
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
|
||||
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
|
||||
+obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
|
||||
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
|
||||
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
|
||||
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -247,6 +247,16 @@ config GPIO_EM
|
||||
help
|
||||
Say yes here to support GPIO on Renesas Emma Mobile SoCs.
|
||||
|
||||
+config GPIO_EN7523
|
||||
+ tristate "Airoha GPIO support"
|
||||
+ depends on ARCH_AIROHA
|
||||
+ default ARCH_AIROHA
|
||||
+ select GPIO_GENERIC
|
||||
+ select GPIOLIB_IRQCHIP
|
||||
+ help
|
||||
+ Say Y or M here to support the GPIO controller block on the
|
||||
+ Airoha EN7523 SoC. It supports two banks of 32 GPIOs.
|
||||
+
|
||||
config GPIO_EP93XX
|
||||
def_bool y
|
||||
depends on ARCH_EP93XX
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o
|
||||
obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
|
||||
obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
|
||||
obj-$(CONFIG_GPIO_EM) += gpio-em.o
|
||||
+obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o
|
||||
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
|
||||
obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
|
||||
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
From 48342ae751c797ac73ac9c894b3f312df18ffd21 Mon Sep 17 00:00:00 2001
|
||||
From: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
Date: Wed, 15 Sep 2021 13:46:20 +0100
|
||||
Subject: [PATCH] ARM: 9124/1: uncompress: Parse "linux,usable-memory-range" DT
|
||||
property
|
||||
|
||||
Add support for parsing the "linux,usable-memory-range" DT property.
|
||||
This property is used to describe the usable memory reserved for the
|
||||
crash dump kernel, and thus makes the memory reservation explicit.
|
||||
If present, Linux no longer needs to mask the program counter, and rely
|
||||
on the "mem=" kernel parameter to obtain the start and size of usable
|
||||
memory.
|
||||
|
||||
For backwards compatibility, the traditional method to derive the start
|
||||
of memory is still used if "linux,usable-memory-range" is absent.
|
||||
|
||||
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
||||
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
|
||||
---
|
||||
.../arm/boot/compressed/fdt_check_mem_start.c | 48 ++++++++++++++++---
|
||||
1 file changed, 42 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/compressed/fdt_check_mem_start.c
|
||||
+++ b/arch/arm/boot/compressed/fdt_check_mem_start.c
|
||||
@@ -55,16 +55,17 @@ static uint64_t get_val(const fdt32_t *c
|
||||
* DTB, and, if out-of-range, replace it by the real start address.
|
||||
* To preserve backwards compatibility (systems reserving a block of memory
|
||||
* at the start of physical memory, kdump, ...), the traditional method is
|
||||
- * always used if it yields a valid address.
|
||||
+ * used if it yields a valid address, unless the "linux,usable-memory-range"
|
||||
+ * property is present.
|
||||
*
|
||||
* Return value: start address of physical memory to use
|
||||
*/
|
||||
uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt)
|
||||
{
|
||||
- uint32_t addr_cells, size_cells, base;
|
||||
+ uint32_t addr_cells, size_cells, usable_base, base;
|
||||
uint32_t fdt_mem_start = 0xffffffff;
|
||||
- const fdt32_t *reg, *endp;
|
||||
- uint64_t size, end;
|
||||
+ const fdt32_t *usable, *reg, *endp;
|
||||
+ uint64_t size, usable_end, end;
|
||||
const char *type;
|
||||
int offset, len;
|
||||
|
||||
@@ -80,6 +81,27 @@ uint32_t fdt_check_mem_start(uint32_t me
|
||||
if (addr_cells > 2 || size_cells > 2)
|
||||
return mem_start;
|
||||
|
||||
+ /*
|
||||
+ * Usable memory in case of a crash dump kernel
|
||||
+ * This property describes a limitation: memory within this range is
|
||||
+ * only valid when also described through another mechanism
|
||||
+ */
|
||||
+ usable = get_prop(fdt, "/chosen", "linux,usable-memory-range",
|
||||
+ (addr_cells + size_cells) * sizeof(fdt32_t));
|
||||
+ if (usable) {
|
||||
+ size = get_val(usable + addr_cells, size_cells);
|
||||
+ if (!size)
|
||||
+ return mem_start;
|
||||
+
|
||||
+ if (addr_cells > 1 && fdt32_ld(usable)) {
|
||||
+ /* Outside 32-bit address space */
|
||||
+ return mem_start;
|
||||
+ }
|
||||
+
|
||||
+ usable_base = fdt32_ld(usable + addr_cells - 1);
|
||||
+ usable_end = usable_base + size;
|
||||
+ }
|
||||
+
|
||||
/* Walk all memory nodes and regions */
|
||||
for (offset = fdt_next_node(fdt, -1, NULL); offset >= 0;
|
||||
offset = fdt_next_node(fdt, offset, NULL)) {
|
||||
@@ -107,7 +129,20 @@ uint32_t fdt_check_mem_start(uint32_t me
|
||||
|
||||
base = fdt32_ld(reg + addr_cells - 1);
|
||||
end = base + size;
|
||||
- if (mem_start >= base && mem_start < end) {
|
||||
+ if (usable) {
|
||||
+ /*
|
||||
+ * Clip to usable range, which takes precedence
|
||||
+ * over mem_start
|
||||
+ */
|
||||
+ if (base < usable_base)
|
||||
+ base = usable_base;
|
||||
+
|
||||
+ if (end > usable_end)
|
||||
+ end = usable_end;
|
||||
+
|
||||
+ if (end <= base)
|
||||
+ continue;
|
||||
+ } else if (mem_start >= base && mem_start < end) {
|
||||
/* Calculated address is valid, use it */
|
||||
return mem_start;
|
||||
}
|
||||
@@ -123,7 +158,8 @@ uint32_t fdt_check_mem_start(uint32_t me
|
||||
}
|
||||
|
||||
/*
|
||||
- * The calculated address is not usable.
|
||||
+ * The calculated address is not usable, or was overridden by the
|
||||
+ * "linux,usable-memory-range" property.
|
||||
* Use the lowest usable physical memory address from the DTB instead,
|
||||
* and make sure this is a multiple of 2 MiB for phys/virt patching.
|
||||
*/
|
||||
|
|
@ -1,341 +0,0 @@
|
|||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -307,6 +307,12 @@ config SPI_DLN2
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called spi-dln2.
|
||||
|
||||
+config SPI_AIROHA_EN7523
|
||||
+ bool "Airoha EN7523 SPI controller support"
|
||||
+ depends on ARCH_AIROHA
|
||||
+ help
|
||||
+ This enables SPI controller support for the Airoha EN7523 SoC.
|
||||
+
|
||||
config SPI_EP93XX
|
||||
tristate "Cirrus Logic EP93xx SPI controller"
|
||||
depends on ARCH_EP93XX || COMPILE_TEST
|
||||
--- a/drivers/spi/Makefile
|
||||
+++ b/drivers/spi/Makefile
|
||||
@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.
|
||||
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
|
||||
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
|
||||
obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
|
||||
+obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o
|
||||
obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
|
||||
obj-$(CONFIG_SPI_FSI) += spi-fsi.o
|
||||
obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/spi/spi-en7523.c
|
||||
@@ -0,0 +1,313 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/mod_devicetable.h>
|
||||
+#include <linux/spi/spi.h>
|
||||
+
|
||||
+
|
||||
+#define ENSPI_READ_IDLE_EN 0x0004
|
||||
+#define ENSPI_MTX_MODE_TOG 0x0014
|
||||
+#define ENSPI_RDCTL_FSM 0x0018
|
||||
+#define ENSPI_MANUAL_EN 0x0020
|
||||
+#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024
|
||||
+#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028
|
||||
+#define ENSPI_MANUAL_OPFIFO_FULL 0x002C
|
||||
+#define ENSPI_MANUAL_OPFIFO_WR 0x0030
|
||||
+#define ENSPI_MANUAL_DFIFO_FULL 0x0034
|
||||
+#define ENSPI_MANUAL_DFIFO_WDATA 0x0038
|
||||
+#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C
|
||||
+#define ENSPI_MANUAL_DFIFO_RD 0x0040
|
||||
+#define ENSPI_MANUAL_DFIFO_RDATA 0x0044
|
||||
+#define ENSPI_IER 0x0090
|
||||
+#define ENSPI_NFI2SPI_EN 0x0130
|
||||
+
|
||||
+// TODO not in spi block
|
||||
+#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4)
|
||||
+
|
||||
+#define OP_CSH 0x00
|
||||
+#define OP_CSL 0x01
|
||||
+#define OP_CK 0x02
|
||||
+#define OP_OUTS 0x08
|
||||
+#define OP_OUTD 0x09
|
||||
+#define OP_OUTQ 0x0A
|
||||
+#define OP_INS 0x0C
|
||||
+#define OP_INS0 0x0D
|
||||
+#define OP_IND 0x0E
|
||||
+#define OP_INQ 0x0F
|
||||
+#define OP_OS2IS 0x10
|
||||
+#define OP_OS2ID 0x11
|
||||
+#define OP_OS2IQ 0x12
|
||||
+#define OP_OD2IS 0x13
|
||||
+#define OP_OD2ID 0x14
|
||||
+#define OP_OD2IQ 0x15
|
||||
+#define OP_OQ2IS 0x16
|
||||
+#define OP_OQ2ID 0x17
|
||||
+#define OP_OQ2IQ 0x18
|
||||
+#define OP_OSNIS 0x19
|
||||
+#define OP_ODNID 0x1A
|
||||
+
|
||||
+#define MATRIX_MODE_AUTO 1
|
||||
+#define CONF_MTX_MODE_AUTO 0
|
||||
+#define MANUALEN_AUTO 0
|
||||
+#define MATRIX_MODE_MANUAL 0
|
||||
+#define CONF_MTX_MODE_MANUAL 9
|
||||
+#define MANUALEN_MANUAL 1
|
||||
+
|
||||
+#define _ENSPI_MAX_XFER 0x1ff
|
||||
+
|
||||
+#define REG(x) (iobase + x)
|
||||
+
|
||||
+
|
||||
+static void __iomem *iobase;
|
||||
+
|
||||
+
|
||||
+static void opfifo_write(u32 cmd, u32 len)
|
||||
+{
|
||||
+ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
|
||||
+
|
||||
+ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
|
||||
+
|
||||
+ /* Wait for room in OPFIFO */
|
||||
+ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
|
||||
+ ;
|
||||
+
|
||||
+ /* Shift command into OPFIFO */
|
||||
+ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
|
||||
+
|
||||
+ /* Wait for command to finish */
|
||||
+ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
|
||||
+ ;
|
||||
+}
|
||||
+
|
||||
+static void set_cs(int state)
|
||||
+{
|
||||
+ if (state)
|
||||
+ opfifo_write(OP_CSH, 1);
|
||||
+ else
|
||||
+ opfifo_write(OP_CSL, 1);
|
||||
+}
|
||||
+
|
||||
+static void manual_begin_cmd(void)
|
||||
+{
|
||||
+ /* Disable read idle state */
|
||||
+ writel(0, REG(ENSPI_READ_IDLE_EN));
|
||||
+
|
||||
+ /* Wait for FSM to reach idle state */
|
||||
+ while (readl(REG(ENSPI_RDCTL_FSM)))
|
||||
+ ;
|
||||
+
|
||||
+ /* Set SPI core to manual mode */
|
||||
+ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
|
||||
+ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
|
||||
+}
|
||||
+
|
||||
+static void manual_end_cmd(void)
|
||||
+{
|
||||
+ /* Set SPI core to auto mode */
|
||||
+ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
|
||||
+ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
|
||||
+
|
||||
+ /* Enable read idle state */
|
||||
+ writel(1, REG(ENSPI_READ_IDLE_EN));
|
||||
+}
|
||||
+
|
||||
+static void dfifo_read(u8 *buf, int len)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < len; i++) {
|
||||
+ /* Wait for requested data to show up in DFIFO */
|
||||
+ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
|
||||
+ ;
|
||||
+ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
|
||||
+ /* Queue up next byte */
|
||||
+ writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void dfifo_write(const u8 *buf, int len)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < len; i++) {
|
||||
+ /* Wait for room in DFIFO */
|
||||
+ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
|
||||
+ ;
|
||||
+ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+#if 0
|
||||
+static void set_spi_clock_speed(int freq_mhz)
|
||||
+{
|
||||
+ u32 tmp, val;
|
||||
+
|
||||
+ tmp = readl(ENSPI_CLOCK_DIVIDER);
|
||||
+ tmp &= 0xffff0000;
|
||||
+ writel(tmp, ENSPI_CLOCK_DIVIDER);
|
||||
+
|
||||
+ val = (400 / (freq_mhz * 2));
|
||||
+ tmp |= (val << 8) | 1;
|
||||
+ writel(tmp, ENSPI_CLOCK_DIVIDER);
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+static void init_hw(void)
|
||||
+{
|
||||
+ /* Disable manual/auto mode clash interrupt */
|
||||
+ writel(0, REG(ENSPI_IER));
|
||||
+
|
||||
+ // TODO via clk framework
|
||||
+ // set_spi_clock_speed(50);
|
||||
+
|
||||
+ /* Disable DMA */
|
||||
+ writel(0, REG(ENSPI_NFI2SPI_EN));
|
||||
+}
|
||||
+
|
||||
+static int xfer_read(struct spi_transfer *xfer)
|
||||
+{
|
||||
+ int opcode;
|
||||
+ uint8_t *buf = xfer->rx_buf;
|
||||
+
|
||||
+ switch (xfer->rx_nbits) {
|
||||
+ case SPI_NBITS_SINGLE:
|
||||
+ opcode = OP_INS;
|
||||
+ break;
|
||||
+ case SPI_NBITS_DUAL:
|
||||
+ opcode = OP_IND;
|
||||
+ break;
|
||||
+ case SPI_NBITS_QUAD:
|
||||
+ opcode = OP_INQ;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ opfifo_write(opcode, xfer->len);
|
||||
+ dfifo_read(buf, xfer->len);
|
||||
+
|
||||
+ return xfer->len;
|
||||
+}
|
||||
+
|
||||
+static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
|
||||
+{
|
||||
+ int opcode;
|
||||
+ const uint8_t *buf = xfer->tx_buf;
|
||||
+
|
||||
+ if (next_xfer_is_rx) {
|
||||
+ /* need to use Ox2Ix opcode to set the core to input afterwards */
|
||||
+ switch (xfer->tx_nbits) {
|
||||
+ case SPI_NBITS_SINGLE:
|
||||
+ opcode = OP_OS2IS;
|
||||
+ break;
|
||||
+ case SPI_NBITS_DUAL:
|
||||
+ opcode = OP_OS2ID;
|
||||
+ break;
|
||||
+ case SPI_NBITS_QUAD:
|
||||
+ opcode = OP_OS2IQ;
|
||||
+ break;
|
||||
+ }
|
||||
+ } else {
|
||||
+ switch (xfer->tx_nbits) {
|
||||
+ case SPI_NBITS_SINGLE:
|
||||
+ opcode = OP_OUTS;
|
||||
+ break;
|
||||
+ case SPI_NBITS_DUAL:
|
||||
+ opcode = OP_OUTD;
|
||||
+ break;
|
||||
+ case SPI_NBITS_QUAD:
|
||||
+ opcode = OP_OUTQ;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ opfifo_write(opcode, xfer->len);
|
||||
+ dfifo_write(buf, xfer->len);
|
||||
+
|
||||
+ return xfer->len;
|
||||
+}
|
||||
+
|
||||
+size_t max_transfer_size(struct spi_device *spi)
|
||||
+{
|
||||
+ return _ENSPI_MAX_XFER;
|
||||
+}
|
||||
+
|
||||
+int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
|
||||
+{
|
||||
+ struct spi_transfer *xfer;
|
||||
+ int next_xfer_is_rx = 0;
|
||||
+
|
||||
+ manual_begin_cmd();
|
||||
+ set_cs(0);
|
||||
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
||||
+ if (xfer->tx_buf) {
|
||||
+ if (!list_is_last(&xfer->transfer_list, &msg->transfers)
|
||||
+ && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
|
||||
+ next_xfer_is_rx = 1;
|
||||
+ else
|
||||
+ next_xfer_is_rx = 0;
|
||||
+ msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
|
||||
+ } else if (xfer->rx_buf) {
|
||||
+ msg->actual_length += xfer_read(xfer);
|
||||
+ }
|
||||
+ }
|
||||
+ set_cs(1);
|
||||
+ manual_end_cmd();
|
||||
+
|
||||
+ msg->status = 0;
|
||||
+ spi_finalize_current_message(ctrl);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int spi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spi_controller *ctrl;
|
||||
+ int err;
|
||||
+
|
||||
+ ctrl = devm_spi_alloc_master(&pdev->dev, 0);
|
||||
+ if (!ctrl) {
|
||||
+ dev_err(&pdev->dev, "Error allocating SPI controller\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
|
||||
+ if (IS_ERR(iobase)) {
|
||||
+ dev_err(&pdev->dev, "Could not map SPI register address");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ init_hw();
|
||||
+
|
||||
+ ctrl->dev.of_node = pdev->dev.of_node;
|
||||
+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
||||
+ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
|
||||
+ ctrl->max_transfer_size = max_transfer_size;
|
||||
+ ctrl->transfer_one_message = transfer_one_message;
|
||||
+ err = devm_spi_register_controller(&pdev->dev, ctrl);
|
||||
+ if (err) {
|
||||
+ dev_err(&pdev->dev, "Could not register SPI controller\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id spi_of_ids[] = {
|
||||
+ { .compatible = "airoha,en7523-spi" },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, spi_of_ids);
|
||||
+
|
||||
+static struct platform_driver spi_driver = {
|
||||
+ .probe = spi_probe,
|
||||
+ .driver = {
|
||||
+ .name = "airoha-en7523-spi",
|
||||
+ .of_match_table = spi_of_ids,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(spi_driver);
|
||||
+
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
|
||||
+MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From b3b76fc86f0fb4d98918f48c784138bfa950dff6 Mon Sep 17 00:00:00 2001
|
||||
From: Felix Fietkau <nbd@nbd.name>
|
||||
Date: Wed, 15 Jun 2022 14:53:34 +0200
|
||||
Subject: [PATCH] PCI: mediatek: Allow building for ARCH_AIROHA
|
||||
|
||||
Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
|
||||
Airoha EN7523 SoC uses the same controller as MT7622.
|
||||
|
||||
The driver itself is not modified. The PCIe controller DT node should use
|
||||
mediatek,mt7622-pcie after airoha,en7523-pcie.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220615125335.96089-2-nbd@nbd.name
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
||||
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
|
||||
---
|
||||
drivers/pci/controller/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/pci/controller/Kconfig
|
||||
+++ b/drivers/pci/controller/Kconfig
|
||||
@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
|
||||
|
||||
config PCIE_MEDIATEK
|
||||
tristate "MediaTek PCIe controller"
|
||||
- depends on ARCH_MEDIATEK || COMPILE_TEST
|
||||
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
|
||||
depends on OF
|
||||
depends on PCI_MSI_IRQ_DOMAIN
|
||||
help
|
||||
Loading…
Reference in New Issue