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lantiq: set port numbers corresponding to reg value

Browse Source 
Fix inconsistencies found in DTS files and sort ethernet ports based on
updated names.

Signed-off-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
[squash two separate patches, rephrase commit title/message]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This commit is contained in:
Aleksander Jan Bajkowski 2020-05-17 12:33:56 +02:00 committed by Adrian Schmutzler
parent 3866fefa38
commit f496939f15
6 changed files with 55 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts
View File

@ -110,30 +110,30 @@
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@4 {
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {

2
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi
View File

@ -105,7 +105,7 @@
phy-handle = <&phy11>;
};
ethernet@3 {
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";

26
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts
View File

@ -162,30 +162,30 @@
reg = <0>;
lantiq,switch;
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "mii";
phy-handle = <&phy11>;
};
ethernet@4 {
ethernet@3 {
compatible = "lantiq,xrx200-pdi-port";
reg = <3>;
phy-mode = "mii";
phy-handle = <&phy12>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "mii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "mii";
phy-handle = <&phy14>;
};
};
mdio {

28
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi
View File

@ -103,17 +103,11 @@
reg = <0>;
lantiq,switch;
ethernet@4 {
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet@1 {
compatible = "lantiq,xrx200-pdi-port";
@ -121,11 +115,17 @@
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
ethernet@0 {
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <0>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
};

14
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi
View File

@ -121,24 +121,24 @@
phy-handle = <&phy0>;
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@3 {
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {

14
target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
View File

@ -41,24 +41,24 @@
phy-handle = <&phy0>;
// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
ethernet@2 {
compatible = "lantiq,xrx200-pdi-port";
reg = <2>;
phy-mode = "gmii";
phy-handle = <&phy11>;
};
ethernet@3 {
ethernet@4 {
compatible = "lantiq,xrx200-pdi-port";
reg = <4>;
phy-mode = "gmii";
phy-handle = <&phy13>;
};
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
};
mdio {